3 from copy
import deepcopy
12 return self
.pins
.has_key(k
)
14 def add_spec(self
, k
, v
):
17 def update(self
, pinidx
, v
):
18 if not self
.pins
.has_key(pinidx
):
21 self
.pins
[pinidx
].update(v
)
24 return self
.pins
.keys()
27 return self
.pins
.items()
35 def __delitem__(self
, k
):
38 def __getitem__(self
, k
):
44 def __init__(self
, fname
, pingroup
, bankspec
, suffix
, offs
, bank
, mux
,
45 spec
=None, limit
=None, origsuffix
=None):
47 # function type can be in, out or inout, represented by - + *
48 # strip function type out of each pin name
50 for i
in range(len(pingroup
)):
55 if fntype
not in '+-*':
58 fntype
= {'-': 'in', '+': 'out', '*': 'inout'}[fntype
]
59 self
.fntype
[pname
] = fntype
63 self
.pingroup
= pingroup
64 self
.bankspec
= bankspec
66 self
.origsuffix
= origsuffix
or suffix
70 # create consistent name suffixes
71 pingroup
= namesuffix(fname
, suffix
, pingroup
)
77 for name
in pingroup
[:limit
]:
79 name_
= "%s_%s" % (name
, suffix
)
82 if spec
and spec
.has_key(name
):
84 pin
= {mux
: (name_
, bank
)}
85 offs_bank
, offs_
= offs
88 idx_
+= bankspec
[bank
]
93 name_
= "%s_%s" % (name
, suffix
)
98 if not spec
.has_key(name
):
100 idx_
, mux_
, bank_
= spec
[name
]
102 pin
= {mux_
: (name_
, bank_
)}
103 if res
.has_key(idx_
):
104 res
[idx_
].update(pin
)
111 def i2s(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
112 i2spins
= ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
114 # i2spins.append("DO%d+" % i)
115 return Pins('IIS', i2spins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
118 def emmc(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
119 emmcpins
= ['CMD+', 'CLK+']
121 emmcpins
.append("D%d*" % i
)
122 return Pins('MMC', emmcpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
125 def sdmmc(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None,
126 start
=None, limit
=None):
127 sdmmcpins
= ['CMD+', 'CLK+']
129 sdmmcpins
.append("D%d*" % i
)
130 sdmmcpins
= sdmmcpins
[start
:limit
]
131 return Pins('SD', sdmmcpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
134 def spi(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
135 spipins
= ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
136 return Pins('SPI', spipins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
139 def quadspi(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
140 spipins
= ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
141 return Pins('QSPI', spipins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
144 def i2c(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
145 spipins
= ['SDA*', 'SCL*']
146 return Pins('TWI', spipins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
149 def jtag(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
150 jtagpins
= ['MS+', 'DI-', 'DO+', 'CK+']
151 return Pins('JTAG', jtagpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
154 def uart(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
155 uartpins
= ['TX+', 'RX-']
156 return Pins('UART', uartpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
159 def namesuffix(name
, suffix
, namelist
):
163 names
.append("%s%s_%s" % (name
, suffix
, n
))
165 names
.append("%s_%s" % (name
, suffix
))
168 def ulpi(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
169 ulpipins
= ['CK+', 'DIR+', 'STP+', 'NXT+']
171 ulpipins
.append('D%d*' % i
)
172 return Pins('ULPI', ulpipins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
175 def uartfull(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
176 uartpins
= ['TX+', 'RX-', 'CTS-', 'RTS+']
177 return Pins('UARTQ', uartpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
180 def rgbttl(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
181 ttlpins
= ['CK+', 'DE+', 'HS+', 'VS+']
183 ttlpins
.append("D%d+" % i
)
184 return Pins('LCD', ttlpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
187 def rgmii(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
190 buspins
.append("ERXD%d-" % i
)
192 buspins
.append("ETXD%d+" % i
)
193 buspins
+= ['ERXCK-', 'ERXERR-', 'ERXDV-',
195 'ETXEN+', 'ETXCK+', 'ECRS-',
197 return Pins('RG', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
200 def flexbus1(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
203 buspins
.append("AD%d*" % i
)
205 buspins
.append("CS%d+" % i
)
206 buspins
+= ['ALE', 'OE', 'RW', 'TA', 'CLK+',
207 'A0', 'A1', 'TS', 'TBST',
210 buspins
.append("BWE%d" % i
)
212 buspins
.append("CS%d+" % i
)
213 return Pins('FB', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
216 def flexbus2(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
218 for i
in range(8,32):
219 buspins
.append("AD%d*" % i
)
220 return Pins('FB', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
223 def sdram1(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
226 buspins
.append("SDRDQM%d*" % i
)
228 buspins
.append("SDRAD%d+" % i
)
230 buspins
.append("SDRDQ%d+" % i
)
232 buspins
.append("SDRCS%d#+" % i
)
234 buspins
.append("SDRDQ%d+" % i
)
236 buspins
.append("SDRBA%d+" % i
)
237 buspins
+= ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
239 return Pins('SDR', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
242 def sdram2(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
245 buspins
.append("SDRCS%d#+" % i
)
246 for i
in range(8,32):
247 buspins
.append("SDRDQ%d*" % i
)
248 return Pins('SDR', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
,
251 def mcu8080(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
254 buspins
.append("MCUD%d*" % i
)
256 buspins
.append("MCUAD%d+" % (i
+8))
258 buspins
.append("MCUCS%d+" % i
)
260 buspins
.append("MCUNRB%d+" % i
)
261 buspins
+= ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
263 return Pins('MCU', buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
266 def _pinbank(bankspec
, prefix
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1,
269 for i
in range(gpiooffs
, gpiooffs
+gpionum
):
270 gpiopins
.append("%s%d*" % (bank
, i
))
271 return Pins(prefix
, gpiopins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
274 def eint(bankspec
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1, spec
=None):
276 for i
in range(gpiooffs
, gpiooffs
+gpionum
):
277 gpiopins
.append("%d*" % (i
))
278 return Pins('EINT', gpiopins
, bankspec
, suffix
, offs
, bank
, mux
, spec
,
281 def pwm(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
282 return Pins('PWM', ['+', ], bankspec
, suffix
, offs
, bank
, mux
, spec
,
285 def gpio(bankspec
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1, spec
=None):
286 return _pinbank(bankspec
, "GPIO%s" % bank
, suffix
, offs
, bank
, gpiooffs
,
287 gpionum
, mux
=0, spec
=None)
289 def pinmerge(pins
, fn
):
290 # hack, store the function specs in the pins dict
292 suffix
= fn
.origsuffix
295 if not hasattr(pins
, 'fnspec'):
299 assert not pins
.has_key('EINT')
300 if not pins
.fnspec
.has_key(fname
):
301 pins
.add_spec(fname
, {})
302 print "fname bank suffix", fname
, bank
, suffix
303 if suffix
or fname
== 'EINT' or fname
== 'PWM':
304 specname
= fname
+ suffix
306 specname
= fname
+ bank
307 if pins
.fnspec
[fname
].has_key(specname
):
308 # ok so some declarations may bring in different
309 # names at different stages (EINT, PWM, flexbus1/2)
310 # so we have to merge the names in. main thing is
312 tomerge
= pins
.fnspec
[fname
][specname
]
313 for p
in fn
.pingroup
:
314 if p
not in tomerge
.pingroup
:
315 tomerge
.pingroup
.append(p
)
316 tomerge
.pins
.update(fn
.pins
)
317 tomerge
.fntype
.update(fn
.fntype
)
319 pins
.fnspec
[fname
][specname
] = deepcopy(fn
)
322 for (pinidx
, v
) in fn
.pins
.items():
323 pins
.update(pinidx
, v
)