src/spec/pinfunctions.py

   1 #!/usr/bin/env python
   2
   3 """ define functions here, with their pin names and the pin type.
   4
   5     each function returns a pair of lists
   6     (or objects with a __getitem__ function)
   7
   8     the first list (or object) contains pin name plus type specifications.
   9
  10     the type is:
  11
  12     * "-" for an input pin,
  13     * "+" for an output pin,
  14     * "*" for an in/out pin
  15
  16     each function is then added to the pinspec tuple, below, as a ("NAME",
  17     function) entry.
  18
  19     different functions may be added multiple times under the same NAME,
  20     so that complex (or large) functions can be split into one or more
  21     groups (and placed on different pinbanks).
  22
  23     eint, pwm and gpio are slightly odd in that instead of a fixed list
  24     an object is returned with a __getitem__ function that accepts a
  25     slice object.  in this way the actual generation of the pin name
  26     is delayed until it is known precisely how many pins are to be
  27     generated, and that's not known immediately (or it would be if
  28     every single one of the functions below had a start and end parameter
  29     added).  see spec.interfaces.PinGen class slice on pingroup
  30
  31     the second list is the names of pins that are part of an inout bus.
  32     this list of pins (a ganged group) will need to be changed under
  33     the control of the function, as a group.  for example: sdmmc's
  34     D0-D3 pins are in-out, they all change from input to output at
  35     the same time under the control of the function, therefore there's
  36     no point having multiple in-out switch/control wires, as the
  37     sdmmc is never going to do anything other than switch this entire
  38     bank all at once.  so in this particular example, sdmmc returns:
  39
  40     (['CMD+', 'CLK+', 'D0*', 'D1*', 'D2*', 'D3*'] # pin names
  41      ['D0*', 'D1*', 'D2*', 'D3*'])                # ganged bus names
  42 """
  43
  44
  45 def i2s(suffix, bank):
  46     return (['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'],
  47             [])
  48
  49
  50 # XXX TODO: correct these.  this is a stub for now
  51 # https://bugs.libre-soc.org/show_bug.cgi?id=303
  52 def lpc(suffix, bank, pincount=4):
  53     lpcpins = ['CMD+', 'CLK+']
  54     inout = []
  55     for i in range(pincount):
  56         pname = "D%d*" % i
  57         lpcpins.append(pname)
  58         inout.append(pname)
  59     return (lpcpins, inout)
  60
  61
  62 def emmc(suffix, bank, pincount=8):
  63     emmcpins = ['CMD+', 'CLK+']
  64     inout = []
  65     for i in range(pincount):
  66         pname = "D%d*" % i
  67         emmcpins.append(pname)
  68         inout.append(pname)
  69     return (emmcpins, inout)
  70
  71
  72 def sdmmc(suffix, bank):
  73     return emmc(suffix, bank, pincount=4)
  74
  75
  76 def nspi(suffix, bank, iosize, masteronly=True):
  77     if masteronly:
  78         qpins = ['CK+', 'NSS+']
  79     else:
  80         qpins = ['CK*', 'NSS*']
  81     inout = []
  82     if iosize == 2:
  83         qpins += ['MOSI+', 'MISO-']
  84     else:
  85         for i in range(iosize):
  86             pname = "IO%d*" % i
  87             qpins.append(pname)
  88             inout.append(pname)
  89     return (qpins, inout)
  90
  91
  92 def mspi(suffix, bank):
  93     return nspi(suffix, bank, 2, masteronly=True)
  94
  95
  96 def mquadspi(suffix, bank):
  97     return nspi(suffix, bank, 4, masteronly=True)
  98
  99
 100 def spi(suffix, bank):
 101     return nspi(suffix, bank, 2)
 102
 103
 104 def quadspi(suffix, bank):
 105     return nspi(suffix, bank, 4)
 106
 107
 108 def i2c(suffix, bank):
 109     return (['SDA*', 'SCL*'], [])
 110
 111
 112 def jtag(suffix, bank):
 113     return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], [])
 114
 115
 116 def uart(suffix, bank):
 117     return (['TX+', 'RX-'], [])
 118
 119
 120 def ulpi(suffix, bank):
 121     ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
 122     for i in range(8):
 123         ulpipins.append('D%d*' % i)
 124     return (ulpipins, [])
 125
 126
 127 def uartfull(suffix, bank):
 128     return (['TX+', 'RX-', 'CTS-', 'RTS+'],
 129             [])
 130
 131
 132 def rgbttl(suffix, bank):
 133     ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
 134     for i in range(24):
 135         ttlpins.append("OUT%d+" % i)
 136     return (ttlpins, [])
 137
 138
 139 def rgmii(suffix, bank):
 140     buspins = []
 141     for i in range(4):
 142         buspins.append("ERXD%d-" % i)
 143     for i in range(4):
 144         buspins.append("ETXD%d+" % i)
 145     buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
 146                 'EMDC+', 'EMDIO*',
 147                 'ETXEN+', 'ETXCK+', 'ECRS-',
 148                 'ECOL+', 'ETXERR+']
 149     return (buspins, [])
 150
 151
 152 def flexbus1(suffix, bank):
 153     buspins = []
 154     inout = []
 155     for i in range(8):
 156         pname = "AD%d*" % i
 157         buspins.append(pname)
 158         inout.append(pname)
 159     for i in range(2):
 160         buspins.append("CS%d+" % i)
 161     buspins += ['ALE+', 'OE+', 'RW+', 'TA-',
 162                 # 'TS+',  commented out for now, mirrors ALE, for mux'd mode
 163                 'TBST+',
 164                 'TSIZ0+', 'TSIZ1+']
 165     for i in range(4):
 166         buspins.append("BWE%d+" % i)
 167     for i in range(2, 6):
 168         buspins.append("CS%d+" % i)
 169     return (buspins, inout)
 170
 171
 172 def flexbus2(suffix, bank):
 173     buspins = []
 174     for i in range(8, 32):
 175         buspins.append("AD%d*" % i)
 176     return (buspins, buspins)
 177
 178
 179 def sdram1(suffix, bank, n_adr=10):
 180     buspins = []
 181     inout = []
 182     for i in range(1):
 183         pname = "DQM%d+" % i
 184         buspins.append(pname)
 185     for i in range(8):
 186         pname = "D%d*" % i
 187         buspins.append(pname)
 188         inout.append(pname)
 189     for i in range(n_adr):
 190         buspins.append("AD%d+" % i)
 191     for i in range(2):
 192         buspins.append("BA%d+" % i)
 193     buspins += ['CLK+', 'CKE+', 'RASn+', 'CASn+', 'WEn+',
 194                 'CSn0+']
 195     return (buspins, inout)
 196
 197
 198 def sdram2(suffix, bank):
 199     buspins = []
 200     inout = []
 201     for i in range(10, 13):
 202         buspins.append("AD%d+" % i)
 203     for i in range(1, 2):
 204         pname = "DQM%d*" % i
 205         buspins.append(pname)
 206     for i in range(8, 16):
 207         pname = "D%d*" % i
 208         buspins.append(pname)
 209         inout.append(pname)
 210     return (buspins, inout)
 211
 212
 213 def sdram3(suffix, bank):
 214     buspins = []
 215     inout = []
 216     for i in range(1, 6):
 217         buspins.append("CSn%d+" % i)
 218     for i in range(13, 14):
 219         buspins.append("AD%d+" % i)
 220     for i in range(1, 4):
 221         pname = "DQM%d*" % i
 222     for i in range(8, 32):
 223         pname = "D%d*" % i
 224         buspins.append(pname)
 225         inout.append(pname)
 226     return (buspins, inout)
 227
 228
 229 def mcu8080(suffix, bank):
 230     buspins = []
 231     inout = []
 232     for i in range(8):
 233         pname = "MCUD%d*" % i
 234         buspins.append(pname)
 235         inout.append(pname)
 236     for i in range(8):
 237         buspins.append("MCUAD%d+" % (i + 8))
 238     for i in range(6):
 239         buspins.append("MCUCS%d+" % i)
 240     for i in range(2):
 241         buspins.append("MCUNRB%d+" % i)
 242     buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
 243                 'MCURST+']
 244     return (buspins, inout)
 245
 246
 247 class RangePin(object):
 248     def __init__(self, suffix, prefix=None):
 249         self.suffix = suffix
 250         self.prefix = prefix or ''
 251
 252     def __getitem__(self, s):
 253         res = []
 254         for idx in range(s.start or 0, s.stop or -1, s.step or 1):
 255             res.append("%s%d%s" % (self.prefix, idx, self.suffix))
 256         return res
 257
 258
 259 def eint(suffix, bank):
 260     return (RangePin("-"), [])
 261
 262
 263 def pwm(suffix, bank):
 264     return (RangePin("+"), [])
 265
 266
 267 def gpio(suffix, bank):
 268     return (("GPIO%s" % bank, RangePin(prefix=bank, suffix="*")), [])
 269
 270 def vss(suffix, bank):
 271     return (RangePin("-"), [])
 272
 273 def vdd(suffix, bank):
 274     return (RangePin("-"), [])
 275
 276 def sys(suffix, bank):
 277     return (['CLK-', 'RST-', 'PLLCLK-', 'PLLOUT+',
 278              'CSEL0-', 'CSEL1-', 'CSEL2-'], [])
 279
 280 # list functions by name here
 281
 282 pinspec = (('IIS', i2s),
 283            ('LPC', lpc),
 284            ('EMMC', emmc),
 285            ('SD', sdmmc),
 286            ('MSPI', mspi),
 287            ('MQSPI', mquadspi),
 288            ('SPI', spi),
 289            ('QSPI', quadspi),
 290            ('TWI', i2c),
 291            ('JTAG', jtag),
 292            ('UART', uart),
 293            ('QUART', uartfull),
 294            ('LCD', rgbttl),
 295            ('ULPI', ulpi),
 296            ('RG', rgmii),
 297            ('FB', flexbus1),
 298            ('FB', flexbus2),
 299            ('SDR', sdram1),
 300            ('SDR', sdram2),
 301            ('SDR', sdram3),
 302            ('VSS', vss),
 303            ('VDD', vdd),
 304            ('SYS', sys),
 305            ('EINT', eint),
 306            ('PWM', pwm),
 307            ('GPIO', gpio),
 308            )