3 """ define functions here, with their pin names and the pin type.
5 each function returns a pair of lists
6 (or objects with a __getitem__ function)
8 the first list (or object) contains pin name plus type specifications.
12 * "-" for an input pin,
13 * "+" for an output pin,
14 * "*" for an in/out pin
16 each function is then added to the pinspec tuple, below, as a ("NAME",
19 different functions may be added multiple times under the same NAME,
20 so that complex (or large) functions can be split into one or more
21 groups (and placed on different pinbanks).
23 eint, pwm and gpio are slightly odd in that instead of a fixed list
24 an object is returned with a __getitem__ function that accepts a
25 slice object. in this way the actual generation of the pin name
26 is delayed until it is known precisely how many pins are to be
27 generated, and that's not known immediately (or it would be if
28 every single one of the functions below had a start and end parameter
29 added). see spec.interfaces.PinGen class slice on pingroup
31 the second list is the names of pins that are part of an inout bus.
32 this list of pins (a ganged group) will need to be changed under
33 the control of the function, as a group. for example: sdmmc's
34 D0-D3 pins are in-out, they all change from input to output at
35 the same time under the control of the function, therefore there's
36 no point having multiple in-out switch/control wires, as the
37 sdmmc is never going to do anything other than switch this entire
38 bank all at once. so in this particular example, sdmmc returns:
40 (['CMD+', 'CLK+', 'D0*', 'D1*', 'D2*', 'D3*'] # pin names
41 ['D0*', 'D1*', 'D2*', 'D3*']) # ganged bus names
45 def i2s(suffix
, bank
):
46 return (['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'],
50 # XXX TODO: correct these. this is a stub for now
51 # https://bugs.libre-soc.org/show_bug.cgi?id=303
52 def lpc(suffix
, bank
, pincount
=4):
53 lpcpins
= ['CMD+', 'CLK+']
55 for i
in range(pincount
):
59 return (lpcpins
, inout
)
62 def emmc(suffix
, bank
, pincount
=8):
63 emmcpins
= ['CMD+', 'CLK+']
65 for i
in range(pincount
):
67 emmcpins
.append(pname
)
69 return (emmcpins
, inout
)
72 def sdmmc(suffix
, bank
):
73 return emmc(suffix
, bank
, pincount
=4)
76 def nspi(suffix
, bank
, iosize
, masteronly
=True):
78 qpins
= ['CK+', 'NSS+']
80 qpins
= ['CK*', 'NSS*']
82 for i
in range(iosize
):
89 def mspi(suffix
, bank
):
90 return nspi(suffix
, bank
, 2, masteronly
=True)
93 def mquadspi(suffix
, bank
):
94 return nspi(suffix
, bank
, 4, masteronly
=True)
97 def spi(suffix
, bank
):
98 return nspi(suffix
, bank
, 2)
101 def quadspi(suffix
, bank
):
102 return nspi(suffix
, bank
, 4)
105 def i2c(suffix
, bank
):
106 return (['SDA*', 'SCL*'], [])
109 def jtag(suffix
, bank
):
110 return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], [])
113 def uart(suffix
, bank
):
114 return (['TX+', 'RX-'], [])
117 def ulpi(suffix
, bank
):
118 ulpipins
= ['CK+', 'DIR+', 'STP+', 'NXT+']
120 ulpipins
.append('D%d*' % i
)
121 return (ulpipins
, [])
124 def uartfull(suffix
, bank
):
125 return (['TX+', 'RX-', 'CTS-', 'RTS+'],
129 def rgbttl(suffix
, bank
):
130 ttlpins
= ['CK+', 'DE+', 'HS+', 'VS+']
132 ttlpins
.append("OUT%d+" % i
)
136 def rgmii(suffix
, bank
):
139 buspins
.append("ERXD%d-" % i
)
141 buspins
.append("ETXD%d+" % i
)
142 buspins
+= ['ERXCK-', 'ERXERR-', 'ERXDV-',
144 'ETXEN+', 'ETXCK+', 'ECRS-',
149 def flexbus1(suffix
, bank
):
154 buspins
.append(pname
)
157 buspins
.append("CS%d+" % i
)
158 buspins
+= ['ALE+', 'OE+', 'RW+', 'TA-',
159 # 'TS+', commented out for now, mirrors ALE, for mux'd mode
163 buspins
.append("BWE%d+" % i
)
164 for i
in range(2, 6):
165 buspins
.append("CS%d+" % i
)
166 return (buspins
, inout
)
169 def flexbus2(suffix
, bank
):
171 for i
in range(8, 32):
172 buspins
.append("AD%d*" % i
)
173 return (buspins
, buspins
)
176 def sdram1(suffix
, bank
):
180 pname
= "SDRDQM%d+" % i
181 buspins
.append(pname
)
183 pname
= "SDRD%d*" % i
184 buspins
.append(pname
)
187 buspins
.append("SDRAD%d+" % i
)
189 buspins
.append("SDRBA%d+" % i
)
190 buspins
+= ['SDRCLK+', 'SDRCKE+', 'SDRRASn+', 'SDRCASn+', 'SDRWEn+',
192 return (buspins
, inout
)
195 def sdram2(suffix
, bank
):
198 for i
in range(1, 6):
199 buspins
.append("SDRCSn%d+" % i
)
200 for i
in range(8, 16):
201 pname
= "SDRDQM%d*" % i
202 buspins
.append(pname
)
203 for i
in range(8, 16):
204 pname
= "SDRD%d*" % i
205 buspins
.append(pname
)
207 return (buspins
, inout
)
210 def sdram3(suffix
, bank
):
213 for i
in range(12, 13):
214 buspins
.append("SDRAD%d+" % i
)
215 for i
in range(8, 64):
216 pname
= "SDRD%d*" % i
217 buspins
.append(pname
)
219 return (buspins
, inout
)
222 def mcu8080(suffix
, bank
):
226 pname
= "MCUD%d*" % i
227 buspins
.append(pname
)
230 buspins
.append("MCUAD%d+" % (i
+ 8))
232 buspins
.append("MCUCS%d+" % i
)
234 buspins
.append("MCUNRB%d+" % i
)
235 buspins
+= ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
237 return (buspins
, inout
)
240 class RangePin(object):
241 def __init__(self
, suffix
, prefix
=None):
243 self
.prefix
= prefix
or ''
245 def __getitem__(self
, s
):
247 for idx
in range(s
.start
or 0, s
.stop
or -1, s
.step
or 1):
248 res
.append("%s%d%s" % (self
.prefix
, idx
, self
.suffix
))
252 def eint(suffix
, bank
):
253 return (RangePin("-"), [])
256 def pwm(suffix
, bank
):
257 return (RangePin("+"), [])
260 def gpio(suffix
, bank
):
261 return (("GPIO%s" % bank
, RangePin(prefix
=bank
, suffix
="*")), [])
264 # list functions by name here
266 pinspec
= (('IIS', i2s
),