bugfix start-point prototype pinmux for LibreSOC 180nm
[pinmux.git] / src / spec / pinfunctions.py
1 #!/usr/bin/env python
2
3 """ define functions here, with their pin names and the pin type.
4
5 each function returns a pair of lists
6 (or objects with a __getitem__ function)
7
8 the first list (or object) contains pin name plus type specifications.
9
10 the type is:
11
12 * "-" for an input pin,
13 * "+" for an output pin,
14 * "*" for an in/out pin
15
16 each function is then added to the pinspec tuple, below, as a ("NAME",
17 function) entry.
18
19 different functions may be added multiple times under the same NAME,
20 so that complex (or large) functions can be split into one or more
21 groups (and placed on different pinbanks).
22
23 eint, pwm and gpio are slightly odd in that instead of a fixed list
24 an object is returned with a __getitem__ function that accepts a
25 slice object. in this way the actual generation of the pin name
26 is delayed until it is known precisely how many pins are to be
27 generated, and that's not known immediately (or it would be if
28 every single one of the functions below had a start and end parameter
29 added). see spec.interfaces.PinGen class slice on pingroup
30
31 the second list is the names of pins that are part of an inout bus.
32 this list of pins (a ganged group) will need to be changed under
33 the control of the function, as a group. for example: sdmmc's
34 D0-D3 pins are in-out, they all change from input to output at
35 the same time under the control of the function, therefore there's
36 no point having multiple in-out switch/control wires, as the
37 sdmmc is never going to do anything other than switch this entire
38 bank all at once. so in this particular example, sdmmc returns:
39
40 (['CMD+', 'CLK+', 'D0*', 'D1*', 'D2*', 'D3*'] # pin names
41 ['D0*', 'D1*', 'D2*', 'D3*']) # ganged bus names
42 """
43
44
45 def i2s(suffix, bank):
46 return (['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'],
47 [])
48
49
50 # XXX TODO: correct these. this is a stub for now
51 # https://bugs.libre-soc.org/show_bug.cgi?id=303
52 def lpc(suffix, bank, pincount=4):
53 lpcpins = ['CMD+', 'CLK+']
54 inout = []
55 for i in range(pincount):
56 pname = "D%d*" % i
57 lpcpins.append(pname)
58 inout.append(pname)
59 return (lpcpins, inout)
60
61
62 def emmc(suffix, bank, pincount=8):
63 emmcpins = ['CMD+', 'CLK+']
64 inout = []
65 for i in range(pincount):
66 pname = "D%d*" % i
67 emmcpins.append(pname)
68 inout.append(pname)
69 return (emmcpins, inout)
70
71
72 def sdmmc(suffix, bank):
73 return emmc(suffix, bank, pincount=4)
74
75
76 def nspi(suffix, bank, iosize, masteronly=True):
77 if masteronly:
78 qpins = ['CK+', 'NSS+']
79 else:
80 qpins = ['CK*', 'NSS*']
81 inout = []
82 for i in range(iosize):
83 pname = "IO%d*" % i
84 qpins.append(pname)
85 inout.append(pname)
86 return (qpins, inout)
87
88
89 def mspi(suffix, bank):
90 return nspi(suffix, bank, 2, masteronly=True)
91
92
93 def mquadspi(suffix, bank):
94 return nspi(suffix, bank, 4, masteronly=True)
95
96
97 def spi(suffix, bank):
98 return nspi(suffix, bank, 2)
99
100
101 def quadspi(suffix, bank):
102 return nspi(suffix, bank, 4)
103
104
105 def i2c(suffix, bank):
106 return (['SDA*', 'SCL*'], [])
107
108
109 def jtag(suffix, bank):
110 return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], [])
111
112
113 def uart(suffix, bank):
114 return (['TX+', 'RX-'], [])
115
116
117 def ulpi(suffix, bank):
118 ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
119 for i in range(8):
120 ulpipins.append('D%d*' % i)
121 return (ulpipins, [])
122
123
124 def uartfull(suffix, bank):
125 return (['TX+', 'RX-', 'CTS-', 'RTS+'],
126 [])
127
128
129 def rgbttl(suffix, bank):
130 ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
131 for i in range(24):
132 ttlpins.append("OUT%d+" % i)
133 return (ttlpins, [])
134
135
136 def rgmii(suffix, bank):
137 buspins = []
138 for i in range(4):
139 buspins.append("ERXD%d-" % i)
140 for i in range(4):
141 buspins.append("ETXD%d+" % i)
142 buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
143 'EMDC+', 'EMDIO*',
144 'ETXEN+', 'ETXCK+', 'ECRS-',
145 'ECOL+', 'ETXERR+']
146 return (buspins, [])
147
148
149 def flexbus1(suffix, bank):
150 buspins = []
151 inout = []
152 for i in range(8):
153 pname = "AD%d*" % i
154 buspins.append(pname)
155 inout.append(pname)
156 for i in range(2):
157 buspins.append("CS%d+" % i)
158 buspins += ['ALE+', 'OE+', 'RW+', 'TA-',
159 # 'TS+', commented out for now, mirrors ALE, for mux'd mode
160 'TBST+',
161 'TSIZ0+', 'TSIZ1+']
162 for i in range(4):
163 buspins.append("BWE%d+" % i)
164 for i in range(2, 6):
165 buspins.append("CS%d+" % i)
166 return (buspins, inout)
167
168
169 def flexbus2(suffix, bank):
170 buspins = []
171 for i in range(8, 32):
172 buspins.append("AD%d*" % i)
173 return (buspins, buspins)
174
175
176 def sdram1(suffix, bank):
177 buspins = []
178 inout = []
179 for i in range(8):
180 pname = "SDRDQM%d+" % i
181 buspins.append(pname)
182 for i in range(8):
183 pname = "SDRD%d*" % i
184 buspins.append(pname)
185 inout.append(pname)
186 for i in range(12):
187 buspins.append("SDRAD%d+" % i)
188 for i in range(2):
189 buspins.append("SDRBA%d+" % i)
190 buspins += ['SDRCLK+', 'SDRCKE+', 'SDRRASn+', 'SDRCASn+', 'SDRWEn+',
191 'SDRCSn0+']
192 return (buspins, inout)
193
194
195 def sdram2(suffix, bank):
196 buspins = []
197 inout = []
198 for i in range(1, 6):
199 buspins.append("SDRCSn%d+" % i)
200 for i in range(8, 16):
201 pname = "SDRDQM%d*" % i
202 buspins.append(pname)
203 for i in range(8, 16):
204 pname = "SDRD%d*" % i
205 buspins.append(pname)
206 inout.append(pname)
207 return (buspins, inout)
208
209
210 def sdram3(suffix, bank):
211 buspins = []
212 inout = []
213 for i in range(12, 13):
214 buspins.append("SDRAD%d+" % i)
215 for i in range(8, 64):
216 pname = "SDRD%d*" % i
217 buspins.append(pname)
218 inout.append(pname)
219 return (buspins, inout)
220
221
222 def mcu8080(suffix, bank):
223 buspins = []
224 inout = []
225 for i in range(8):
226 pname = "MCUD%d*" % i
227 buspins.append(pname)
228 inout.append(pname)
229 for i in range(8):
230 buspins.append("MCUAD%d+" % (i + 8))
231 for i in range(6):
232 buspins.append("MCUCS%d+" % i)
233 for i in range(2):
234 buspins.append("MCUNRB%d+" % i)
235 buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
236 'MCURST+']
237 return (buspins, inout)
238
239
240 class RangePin(object):
241 def __init__(self, suffix, prefix=None):
242 self.suffix = suffix
243 self.prefix = prefix or ''
244
245 def __getitem__(self, s):
246 res = []
247 for idx in range(s.start or 0, s.stop or -1, s.step or 1):
248 res.append("%s%d%s" % (self.prefix, idx, self.suffix))
249 return res
250
251
252 def eint(suffix, bank):
253 return (RangePin("-"), [])
254
255
256 def pwm(suffix, bank):
257 return (RangePin("+"), [])
258
259
260 def gpio(suffix, bank):
261 return (("GPIO%s" % bank, RangePin(prefix=bank, suffix="*")), [])
262
263
264 # list functions by name here
265
266 pinspec = (('IIS', i2s),
267 ('LPC', lpc),
268 ('EMMC', emmc),
269 ('MMC', sdmmc),
270 ('MSPI', mspi),
271 ('MQSPI', mquadspi),
272 ('SPI', spi),
273 ('QSPI', quadspi),
274 ('TWI', i2c),
275 ('JTAG', jtag),
276 ('UART', uart),
277 ('QUART', uartfull),
278 ('LCD', rgbttl),
279 ('ULPI', ulpi),
280 ('RG', rgmii),
281 ('FB', flexbus1),
282 ('FB', flexbus2),
283 ('SDR', sdram1),
284 ('SDR', sdram2),
285 ('SDR', sdram3),
286 ('EINT', eint),
287 ('PWM', pwm),
288 ('GPIO', gpio),
289 )