1 from nmutil
.iocontrol
import RecordObject
2 from nmigen
import Signal
3 from svstate
import SVSTATERec
6 class CoreState(RecordObject
):
7 """contains "Core State Information" which says exactly where things are
9 example: eint says to PowerDecoder that it should fire an exception
10 rather than let the current decoded instruction proceed. likewise
11 if dec goes negative. MSR contains LE/BE and Priv state. PC contains
12 the Program Counter, and SVSTATE is the Sub-Program-Counter.
14 def __init__(self
, name
):
15 super().__init
__(name
=name
)
16 self
.pc
= Signal(64) # Program Counter (CIA, NIA)
17 self
.msr
= Signal(64) # Machine Status Register (MSR)
18 self
.eint
= Signal() # External Interrupt
19 self
.dec
= Signal(64) # DEC SPR (again, for interrupt generation)
20 self
.svstate
= SVSTATERec(name
) # Simple-V SVSTATE