1 """JTAG test copied from soc/debug/test/test_jtag_tap_srv.py
2 Trying to avoid using soc modules here
4 based on Staf Verhaegen (Chips4Makers) wishbone TAP
8 from nmigen
import (Module
, Signal
, Elaboratable
, Const
)
9 from c4m
.nmigen
.jtag
.tap
import TAP
, IOType
10 from c4m
.nmigen
.jtag
.bus
import Interface
as JTAGInterface
11 from soc
.debug
.dmi
import DMIInterface
, DBGCore
12 from soc
.debug
.test
.dmi_sim
import dmi_sim
13 from jtag
import JTAG
, resiotypes
14 from soc
.debug
.test
.jtagremote
import JTAGServer
, JTAGClient
16 from soc
.bus
.sram
import SRAM
17 from nmigen
import Memory
, Signal
, Module
19 from nmigen
.sim
import Simulator
, Delay
, Settle
, Tick
20 from nmutil
.util
import wrap
21 from soc
.debug
.jtagutils
import (jtag_read_write_reg
,
22 jtag_srv
, jtag_set_reset
,
23 jtag_set_ir
, jtag_set_get_dr
)
27 # in, out, tri-out, tri-inout
28 'test': ['io0-', 'io1+', 'io2>', 'io3*'],
32 # JTAG-ircodes for accessing DMI
37 # JTAG-ircodes for accessing Wishbone
42 # JTAG boundary scan reg addresses
49 def jtag_sim(dut
, srv_dut
):
51 ####### JTAGy stuff (IDCODE) ######
54 yield from jtag_set_reset(dut
)
55 idcode
= yield from jtag_read_write_reg(dut
, 0b1, 32)
56 print ("idcode", hex(idcode
))
57 assert idcode
== 0x18ff
59 ####### JTAG Boundary scan ######
62 print ("scan len", bslen
)
66 yield srv_dut
.ios
[0].pad
.i
.eq(1)
67 yield srv_dut
.ios
[1].core
.o
.eq(0)
68 yield srv_dut
.ios
[2].core
.o
.eq(1)
69 yield srv_dut
.ios
[2].core
.oe
.eq(1)
70 yield srv_dut
.ios
[3].pad
.i
.eq(0)
71 yield srv_dut
.ios
[3].core
.o
.eq(0)
72 yield srv_dut
.ios
[3].core
.oe
.eq(1)
75 bs
= yield from jtag_read_write_reg(dut
, BS_SAMPLE
, bslen
, bs_actual
)
76 print ("bs scan", bin(bs
))
79 print ("io0 pad.i", (yield srv_dut
.ios
[0].core
.i
))
80 print ("io1 core.o", (yield srv_dut
.ios
[1].pad
.o
))
81 print ("io2 core.o", (yield srv_dut
.ios
[2].pad
.o
))
82 print ("io2 core.oe", (yield srv_dut
.ios
[2].pad
.oe
))
83 print ("io3 core.i", (yield srv_dut
.ios
[3].core
.i
))
84 print ("io3 pad.o", (yield srv_dut
.ios
[3].pad
.o
))
85 print ("io3 pad.oe", (yield srv_dut
.ios
[3].pad
.oe
))
87 assert (yield srv_dut
.ios
[0].core
.i
) == 1
88 assert (yield srv_dut
.ios
[1].pad
.o
) == 0
89 assert (yield srv_dut
.ios
[2].pad
.o
) == 1
90 assert (yield srv_dut
.ios
[2].pad
.oe
) == 1
91 assert (yield srv_dut
.ios
[3].core
.i
) == 0
92 assert (yield srv_dut
.ios
[3].pad
.o
) == 0
93 assert (yield srv_dut
.ios
[3].pad
.oe
) == 1
96 ir_actual
= yield from jtag_set_ir(dut
, BS_EXTEST
)
97 print ("ir extest", bin(ir_actual
))
100 print ("io0 pad.i", (yield srv_dut
.ios
[0].core
.i
))
101 print ("io1 core.o", (yield srv_dut
.ios
[1].pad
.o
))
102 print ("io2 core.o", (yield srv_dut
.ios
[2].pad
.o
))
103 print ("io2 core.oe", (yield srv_dut
.ios
[2].pad
.oe
))
104 print ("io3 core.i", (yield srv_dut
.ios
[3].core
.i
))
105 print ("io3 pad.o", (yield srv_dut
.ios
[3].pad
.o
))
106 print ("io3 pad.oe", (yield srv_dut
.ios
[3].pad
.oe
))
108 assert (yield srv_dut
.ios
[0].core
.i
) == 0
109 assert (yield srv_dut
.ios
[1].pad
.o
) == 1
110 assert (yield srv_dut
.ios
[2].pad
.o
) == 0
111 assert (yield srv_dut
.ios
[2].pad
.oe
) == 0
112 assert (yield srv_dut
.ios
[3].core
.i
) == 1
113 assert (yield srv_dut
.ios
[3].pad
.o
) == 1
114 assert (yield srv_dut
.ios
[3].pad
.oe
) == 0
117 bs_actual
= 0b1011001
118 yield srv_dut
.ios
[0].pad
.i
.eq(0)
119 yield srv_dut
.ios
[1].core
.o
.eq(1)
120 yield srv_dut
.ios
[2].core
.o
.eq(0)
121 yield srv_dut
.ios
[2].core
.oe
.eq(0)
122 yield srv_dut
.ios
[3].pad
.i
.eq(1)
123 yield srv_dut
.ios
[3].core
.o
.eq(1)
124 yield srv_dut
.ios
[3].core
.oe
.eq(0)
127 bs
= yield from jtag_set_get_dr(dut
, bslen
, bs_actual
)
128 print ("bs scan", bin(bs
))
131 print ("io0 pad.i", (yield srv_dut
.ios
[0].core
.i
))
132 print ("io1 core.o", (yield srv_dut
.ios
[1].pad
.o
))
133 print ("io2 core.o", (yield srv_dut
.ios
[2].pad
.o
))
134 print ("io2 core.oe", (yield srv_dut
.ios
[2].pad
.oe
))
135 print ("io3 core.i", (yield srv_dut
.ios
[3].core
.i
))
136 print ("io3 pad.o", (yield srv_dut
.ios
[3].pad
.o
))
137 print ("io3 pad.oe", (yield srv_dut
.ios
[3].pad
.oe
))
139 assert (yield srv_dut
.ios
[0].core
.i
) == 1
140 assert (yield srv_dut
.ios
[1].pad
.o
) == 0
141 assert (yield srv_dut
.ios
[2].pad
.o
) == 1
142 assert (yield srv_dut
.ios
[2].pad
.oe
) == 1
143 assert (yield srv_dut
.ios
[3].core
.i
) == 0
144 assert (yield srv_dut
.ios
[3].pad
.o
) == 0
145 assert (yield srv_dut
.ios
[3].pad
.oe
) == 1
148 yield from jtag_set_reset(dut
)
152 print ("io0 pad.i", (yield srv_dut
.ios
[0].pad
.i
))
153 print ("io1 core.o", (yield srv_dut
.ios
[1].core
.o
))
154 print ("io2 core.o", (yield srv_dut
.ios
[2].core
.o
))
155 print ("io2 core.oe", (yield srv_dut
.ios
[2].core
.oe
))
156 print ("io3 core.i", (yield srv_dut
.ios
[3].core
.i
))
157 print ("io3 pad.o", (yield srv_dut
.ios
[3].pad
.o
))
158 print ("io3 pad.oe", (yield srv_dut
.ios
[3].pad
.oe
))
160 assert (yield srv_dut
.ios
[0].core
.i
) == 0
161 assert (yield srv_dut
.ios
[1].pad
.o
) == 1
162 assert (yield srv_dut
.ios
[2].pad
.o
) == 0
163 assert (yield srv_dut
.ios
[2].pad
.oe
) == 0
164 assert (yield srv_dut
.ios
[3].core
.i
) == 1
165 assert (yield srv_dut
.ios
[3].pad
.o
) == 1
166 assert (yield srv_dut
.ios
[3].pad
.oe
) == 0
168 ####### JTAG to DMI ######
171 yield from jtag_read_write_reg(dut
, DMI_ADDR
, 8, DBGCore
.CTRL
)
173 # read DMI CTRL register
174 status
= yield from jtag_read_write_reg(dut
, DMI_READ
, 64)
175 print ("dmi ctrl status", hex(status
))
179 yield from jtag_read_write_reg(dut
, DMI_ADDR
, 8, 0)
181 # write DMI CTRL register
182 status
= yield from jtag_read_write_reg(dut
, DMI_WRRD
, 64, 0b101)
183 print ("dmi ctrl status", hex(status
))
184 assert status
== 4 # returned old value (nice! cool feature!)
187 yield from jtag_read_write_reg(dut
, DMI_ADDR
, 8, DBGCore
.CTRL
)
189 # read DMI CTRL register
190 status
= yield from jtag_read_write_reg(dut
, DMI_READ
, 64)
191 print ("dmi ctrl status", hex(status
))
194 # write DMI MSR address
195 yield from jtag_read_write_reg(dut
, DMI_ADDR
, 8, DBGCore
.MSR
)
197 # read DMI MSR register
198 msr
= yield from jtag_read_write_reg(dut
, DMI_READ
, 64)
199 print ("dmi msr", hex(msr
))
200 assert msr
== 0xdeadbeef
202 ####### JTAG to Wishbone ######
204 # write Wishbone address
205 yield from jtag_read_write_reg(dut
, WB_ADDR
, 64, 0x18)
207 # write/read wishbone data
208 data
= yield from jtag_read_write_reg(dut
, WB_WRRD
, 64, 0xfeef)
209 print ("wb write", hex(data
))
211 # write Wishbone address
212 yield from jtag_read_write_reg(dut
, WB_ADDR
, 64, 0x18)
214 # write/read wishbone data
215 data
= yield from jtag_read_write_reg(dut
, WB_READ
, 64, 0)
216 print ("wb read", hex(data
))
218 ####### done - tell dmi_sim to stop (otherwise it won't) ########
221 print ("jtag sim stopping")
224 if __name__
== '__main__':
225 # Not sure if need to specify wb_data width here
226 dut
= JTAG(test_pinset(), "sync") # , wb_data_wid=64)
229 # rather than the client access the JTAG bus directly
230 # create an alternative that the client sets
233 cdut
.cbus
= JTAGInterface()
235 # set up client-server on port 44843-something
237 if len(sys
.argv
) != 2 or sys
.argv
[1] != 'server':
238 cdut
.c
= JTAGClient()
239 dut
.s
.get_connection()
241 dut
.s
.get_connection(None) # block waiting for connection
243 # take copy of ir_width and scan_len
244 cdut
._ir
_width
= dut
._ir
_width
245 cdut
.scan_len
= dut
.scan_len
247 #memory = Memory(width=64, depth=16)
248 #sram = SRAM(memory=memory, bus=dut.wb)
251 m
.submodules
.ast
= dut
252 #m.submodules.sram = sram
255 sim
.add_clock(1e-6, domain
="sync") # standard clock
257 sim
.add_sync_process(wrap(jtag_srv(dut
))) # jtag server
258 if len(sys
.argv
) != 2 or sys
.argv
[1] != 'server':
259 sim
.add_sync_process(wrap(jtag_sim(cdut
, dut
))) # actual jtag tester
261 print ("running server only as requested, use openocd remote to test")
262 sim
.add_sync_process(wrap(dmi_sim(dut
))) # handles (pretends to be) DMI
264 with sim
.write_vcd("dmi2jtag_test_srv.vcd"):