3 This BSV file has been generated by the PinMux tool available at:
4 https://bitbucket.org/casl/pinmux.
6 Authors: Neel Gala, Luke
7 Date of generation: Sun Jul 22 05:31:10 2018
10 package pinmux_experiment;
14 (*always_ready,always_enabled*)
15 interface MuxSelectionLines;
17 // declare the method which will capture the user pin-mux
18 // selection values.The width of the input is dependent on the number
19 // of muxes happening per IO. For now we have a generalized width
20 // where each IO will have the same number of muxes.
21 method Action cell0_mux (Bit#(2) in);
22 method Action cell1_mux (Bit#(2) in);
23 method Action cell2_mux (Bit#(2) in);
28 // declare the interface to the IO cells.
29 // Each IO cell will have 1 input field (output from pin mux)
30 // and an output and out-enable field (input to pinmux)
31 // interface declaration between IO-0 and pinmux
32 (*always_ready,always_enabled*) method Bit#(1) io0_cell_out;
33 (*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
34 (*always_ready,always_enabled,result="io"*) method
35 Action io0_cell_in (Bit#(1) in);
36 // interface declaration between IO-1 and pinmux
37 (*always_ready,always_enabled*) method Bit#(1) io1_cell_out;
38 (*always_ready,always_enabled*) method Bit#(1) io1_cell_outen;
39 (*always_ready,always_enabled,result="io"*) method
40 Action io1_cell_in (Bit#(1) in);
41 // interface declaration between IO-2 and pinmux
42 (*always_ready,always_enabled*) method Bit#(1) io2_cell_out;
43 (*always_ready,always_enabled*) method Bit#(1) io2_cell_outen;
44 (*always_ready,always_enabled,result="io"*) method
45 Action io2_cell_in (Bit#(1) in);
48 // interface declaration between UART and pinmux
49 (*always_ready,always_enabled*)
50 interface PeripheralSideUART;
51 interface Put#(Bit#(1)) tx;
52 interface Get#(Bit#(1)) rx;
55 // interface declaration between GPIOA and pinmux
56 (*always_ready,always_enabled*)
57 interface PeripheralSideGPIOA;
58 interface Put#(Bit#(1)) a0_out;
59 interface Put#(Bit#(1)) a0_outen;
60 interface Get#(Bit#(1)) a0_in;
61 interface Put#(Bit#(1)) a1_out;
62 interface Put#(Bit#(1)) a1_outen;
63 interface Get#(Bit#(1)) a1_in;
64 interface Put#(Bit#(1)) a2_out;
65 interface Put#(Bit#(1)) a2_outen;
66 interface Get#(Bit#(1)) a2_in;
69 // interface declaration between TWI and pinmux
70 (*always_ready,always_enabled*)
71 interface PeripheralSideTWI;
72 interface Put#(Bit#(1)) sda_out;
73 interface Put#(Bit#(1)) sda_outen;
74 interface Get#(Bit#(1)) sda_in;
75 interface Put#(Bit#(1)) scl_out;
76 interface Put#(Bit#(1)) scl_outen;
77 interface Get#(Bit#(1)) scl_in;
80 (*always_ready,always_enabled*)
81 interface PeripheralSide;
82 // declare the interface to the peripherals
83 // Each peripheral's function will be either an input, output
84 // or be bi-directional. an input field will be an output from the
85 // peripheral and an output field will be an input to the peripheral.
86 // Bi-directional functions also have an output-enable (which
87 // again comes *in* from the peripheral)
88 interface PeripheralSideUART uart;
89 interface PeripheralSideGPIOA gpioa;
90 interface PeripheralSideTWI twi;
95 // this interface controls how each IO cell is routed. setting
96 // any given IO cell's mux control value will result in redirection
97 // of not just the input or output to different peripheral functions
98 // but also the *direction* control - if appropriate - as well.
99 interface MuxSelectionLines mux_lines;
101 // this interface contains the inputs, outputs and direction-control
102 // lines for all peripherals. GPIO is considered to also be just
103 // a peripheral because it also has in, out and direction-control.
104 interface PeripheralSide peripheral_side;
106 // this interface is to be linked to the individual IO cells.
107 // if looking at a "non-muxed" GPIO design, basically the
108 // IO cell input, output and direction-control wires are cut
109 // (giving six pairs of dangling wires, named left and right)
110 // these iocells are routed in their place on one side ("left")
111 // and the matching *GPIO* peripheral interfaces in/out/dir
112 // connect to the OTHER side ("right"). the result is that
113 // the muxer settings end up controlling the routing of where
114 // the I/O from the IOcell actually goes.
115 interface IOCellSide iocell_side;
119 module mkpinmux(Ifc_pinmux);
121 // the followins wires capture the pin-mux selection
122 // values for each mux assigned to a CELL
124 Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
125 Wire#(Bit#(2)) wrcell1_mux<-mkDWire(0);
126 Wire#(Bit#(2)) wrcell2_mux<-mkDWire(0);
127 // following wires capture signals to IO CELL if io-0 is
129 Wire#(Bit#(1)) cell0_mux_out<-mkDWire(0);
130 Wire#(Bit#(1)) cell0_mux_outen<-mkDWire(0);
131 Wire#(Bit#(1)) cell0_mux_in<-mkDWire(0);
133 // following wires capture signals to IO CELL if io-1 is
135 Wire#(Bit#(1)) cell1_mux_out<-mkDWire(0);
136 Wire#(Bit#(1)) cell1_mux_outen<-mkDWire(0);
137 Wire#(Bit#(1)) cell1_mux_in<-mkDWire(0);
139 // following wires capture signals to IO CELL if io-2 is
141 Wire#(Bit#(1)) cell2_mux_out<-mkDWire(0);
142 Wire#(Bit#(1)) cell2_mux_outen<-mkDWire(0);
143 Wire#(Bit#(1)) cell2_mux_in<-mkDWire(0);
145 // following wires capture signals to IO CELL if uart-0 is
147 Wire#(Bit#(1)) wruart_tx<-mkDWire(0);
148 Wire#(Bit#(1)) wruart_rx<-mkDWire(0);
150 // following wires capture signals to IO CELL if gpioa-0 is
152 Wire#(Bit#(1)) wrgpioa_a0_out<-mkDWire(0);
153 Wire#(Bit#(1)) wrgpioa_a0_outen<-mkDWire(0);
154 Wire#(Bit#(1)) wrgpioa_a0_in<-mkDWire(0);
155 Wire#(Bit#(1)) wrgpioa_a1_out<-mkDWire(0);
156 Wire#(Bit#(1)) wrgpioa_a1_outen<-mkDWire(0);
157 Wire#(Bit#(1)) wrgpioa_a1_in<-mkDWire(0);
158 Wire#(Bit#(1)) wrgpioa_a2_out<-mkDWire(0);
159 Wire#(Bit#(1)) wrgpioa_a2_outen<-mkDWire(0);
160 Wire#(Bit#(1)) wrgpioa_a2_in<-mkDWire(0);
162 // following wires capture signals to IO CELL if twi-0 is
164 Wire#(Bit#(1)) wrtwi_sda_out<-mkDWire(0);
165 Wire#(Bit#(1)) wrtwi_sda_outen<-mkDWire(0);
166 Wire#(Bit#(1)) wrtwi_sda_in<-mkDWire(0);
167 Wire#(Bit#(1)) wrtwi_scl_out<-mkDWire(0);
168 Wire#(Bit#(1)) wrtwi_scl_outen<-mkDWire(0);
169 Wire#(Bit#(1)) wrtwi_scl_in<-mkDWire(0);
172 /*====== This where the muxing starts for each io-cell======*/
173 Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
174 // output muxer for cell idx 0
176 wrcell0_mux==0?wrgpioa_a0_out:
177 wrcell0_mux==1?wruart_tx:
178 wrcell0_mux==2?val0: // unused
181 // outen muxer for cell idx 0
183 wrcell0_mux==0?wrgpioa_a0_outen: // bi-directional
184 wrcell0_mux==1?wrgpioa_a0_outen: // uart_tx is an output
185 wrcell0_mux==2?val0: // unused
186 wrtwi_sda_outen; // bi-directional
188 // priority-in-muxer for cell idx 0
189 rule assign_wrgpioa_a0_in_on_cell0(wrcell0_mux==0);
190 wrgpioa_a0_in<=cell0_mux_in;
193 rule assign_wrtwi_sda_in_on_cell0(wrcell0_mux==3);
194 wrtwi_sda_in<=cell0_mux_in;
197 // output muxer for cell idx 1
199 wrcell1_mux==0?wrgpioa_a1_out:
200 wrcell1_mux==1?val0: // uart_rx is an input
201 wrcell1_mux==2?wrtwi_sda_out:
204 // outen muxer for cell idx 1
206 wrcell1_mux==0?wrgpioa_a1_outen: // bi-directional
207 wrcell1_mux==1?val0: // uart_rx is an input
208 wrcell1_mux==2?wrtwi_sda_outen: // bi-directional
211 // priority-in-muxer for cell idx 1
212 rule assign_wrgpioa_a1_in_on_cell1(wrcell1_mux==0);
213 wrgpioa_a1_in<=cell1_mux_in;
216 rule assign_wruart_rx_on_cell1(wrcell1_mux==1);
217 wruart_rx<=cell1_mux_in;
220 rule assign_wrtwi_sda_in_on_cell1(wrcell1_mux==2);
221 wrtwi_sda_in<=cell1_mux_in;
224 // output muxer for cell idx 2
226 wrcell2_mux==0?wrgpioa_a2_out:
227 wrcell2_mux==1?val0: // unused
228 wrcell2_mux==2?wrtwi_scl_out:
231 // outen muxer for cell idx 2
233 wrcell2_mux==0?wrgpioa_a2_outen: // bi-directional
234 wrcell2_mux==1?val0: // unused
235 wrcell2_mux==2?wrtwi_scl_outen: // bi-directional
238 // priority-in-muxer for cell idx 2
239 rule assign_wrgpioa_a2_in_on_cell2(wrcell2_mux==0);
240 wrgpioa_a2_in<=cell2_mux_in;
243 rule assign_wrtwi_scl_in_on_cell2(wrcell2_mux==2);
244 wrtwi_scl_in<=cell2_mux_in;
248 /*=========================================*/
252 /*============================================================*/
254 interface mux_lines = interface MuxSelectionLines
256 method Action cell0_mux(Bit#(2) in);
260 method Action cell1_mux(Bit#(2) in);
264 method Action cell2_mux(Bit#(2) in);
270 interface iocell_side = interface IOCellSide
272 method io0_cell_out=cell0_mux_out;
273 method io0_cell_outen=cell0_mux_outen;
274 method Action io0_cell_in(Bit#(1) in);
278 method io1_cell_out=cell1_mux_out;
279 method io1_cell_outen=cell1_mux_outen;
280 method Action io1_cell_in(Bit#(1) in);
284 method io2_cell_out=cell2_mux_out;
285 method io2_cell_outen=cell2_mux_outen;
286 method Action io2_cell_in(Bit#(1) in);
292 interface peripheral_side = interface PeripheralSide
293 interface uart = interface PeripheralSideUART
294 interface tx = interface Put
295 method Action put(Bit#(1) in);
299 interface rx = interface Get
300 method ActionValue#(Bit#(1)) get;
306 interface gpioa = interface PeripheralSideGPIOA
307 interface a0_out = interface Put
308 method Action put(Bit#(1) in);
312 interface a0_outen = interface Put
313 method Action put(Bit#(1) in);
314 wrgpioa_a0_outen<=in;
317 interface a0_in = interface Get
318 method ActionValue#(Bit#(1)) get;
319 return wrgpioa_a0_in;
322 interface a1_out = interface Put
323 method Action put(Bit#(1) in);
327 interface a1_outen = interface Put
328 method Action put(Bit#(1) in);
329 wrgpioa_a1_outen<=in;
332 interface a1_in = interface Get
333 method ActionValue#(Bit#(1)) get;
334 return wrgpioa_a1_in;
337 interface a2_out = interface Put
338 method Action put(Bit#(1) in);
342 interface a2_outen = interface Put
343 method Action put(Bit#(1) in);
344 wrgpioa_a2_outen<=in;
347 interface a2_in = interface Get
348 method ActionValue#(Bit#(1)) get;
349 return wrgpioa_a2_in;
354 interface twi = interface PeripheralSideTWI
355 interface sda_out = interface Put
356 method Action put(Bit#(1) in);
360 interface sda_outen = interface Put
361 method Action put(Bit#(1) in);
365 interface sda_in = interface Get
366 method ActionValue#(Bit#(1)) get;
370 interface scl_out = interface Put
371 method Action put(Bit#(1) in);
375 interface scl_outen = interface Put
376 method Action put(Bit#(1) in);
380 interface scl_in = interface Get
381 method ActionValue#(Bit#(1)) get;