src/test_bsv/pinmux_experiment.bsv

   1
   2 /*
   3    This BSV file has been generated by the PinMux tool available at:
   4    https://bitbucket.org/casl/pinmux.
   5
   6    Authors: Neel Gala, Luke
   7    Date of generation: Sun Jul 22 05:31:10 2018
   8 */
   9
  10 package pinmux;
  11
  12    interface MuxSelectionLines;
  13
  14       // declare the method which will capture the user pin-mux
  15       // selection values.The width of the input is dependent on the number
  16       // of muxes happening per IO. For now we have a generalized width
  17       // where each IO will have the same number of muxes.
  18      method  Action cell0_mux (Bit#(2) in);
  19      method  Action cell1_mux (Bit#(2) in);
  20      method  Action cell2_mux (Bit#(2) in);
  21       endinterface
  22
  23
  24       interface IOCellSide;
  25       // declare the interface to the IO cells.
  26       // Each IO cell will have 1 input field (output from pin mux)
  27       // and an output and out-enable field (input to pinmux)
  28           // interface declaration between IO-0 and pinmux
  29     (*always_ready,always_enabled*) method  Bit#(1) io0_cell_out;
  30     (*always_ready,always_enabled*) method  Bit#(1) io0_cell_outen;
  31     (*always_ready,always_enabled,result="io"*) method
  32                        Action io0_cell_in (Bit#(1) in);
  33           // interface declaration between IO-1 and pinmux
  34     (*always_ready,always_enabled*) method  Bit#(1) io1_cell_out;
  35     (*always_ready,always_enabled*) method  Bit#(1) io1_cell_outen;
  36     (*always_ready,always_enabled,result="io"*) method
  37                        Action io1_cell_in (Bit#(1) in);
  38           // interface declaration between IO-2 and pinmux
  39     (*always_ready,always_enabled*) method  Bit#(1) io2_cell_out;
  40     (*always_ready,always_enabled*) method  Bit#(1) io2_cell_outen;
  41     (*always_ready,always_enabled,result="io"*) method
  42                        Action io2_cell_in (Bit#(1) in);
  43       endinterface
  44
  45
  46       interface PeripheralSideUART;
  47           // interface declaration between UART and pinmux
  48     (*always_ready,always_enabled*) method  Action tx (Bit#(1) in);
  49     (*always_ready,always_enabled*) method  Bit#(1) rx;
  50       endinterface
  51
  52       interface PeripheralSideGPIOA;
  53           // interface declaration between GPIOA-0 and pinmux
  54     (*always_ready,always_enabled*) method  Action a0_out (Bit#(1) in);
  55     (*always_ready,always_enabled*) method  Action a0_outen (Bit#(1) in);
  56     (*always_ready,always_enabled*) method  Bit#(1) a0_in;
  57     (*always_ready,always_enabled*) method  Action a1_out (Bit#(1) in);
  58     (*always_ready,always_enabled*) method  Action a1_outen (Bit#(1) in);
  59     (*always_ready,always_enabled*) method  Bit#(1) a1_in;
  60     (*always_ready,always_enabled*) method  Action a2_out (Bit#(1) in);
  61     (*always_ready,always_enabled*) method  Action a2_outen (Bit#(1) in);
  62     (*always_ready,always_enabled*) method  Bit#(1) a2_in;
  63         endinterface
  64
  65       interface PeripheralSideTWI;
  66           // interface declaration between TWI and pinmux
  67     (*always_ready,always_enabled*) method  Action sda_out (Bit#(1) in);
  68     (*always_ready,always_enabled*) method  Action sda_outen (Bit#(1) in);
  69     (*always_ready,always_enabled*) method  Bit#(1) sda_in;
  70     (*always_ready,always_enabled*) method  Action scl_out (Bit#(1) in);
  71     (*always_ready,always_enabled*) method  Action scl_outen (Bit#(1) in);
  72     (*always_ready,always_enabled*) method  Bit#(1) scl_in;
  73       endinterface
  74
  75       interface PeripheralSide;
  76       // declare the interface to the peripherals
  77       // Each peripheral's function will be either an input, output
  78       // or be bi-directional.  an input field will be an output from the
  79       // peripheral and an output field will be an input to the peripheral.
  80       // Bi-directional functions also have an output-enable (which
  81       // again comes *in* from the peripheral)
  82           // interface declaration between UART-0 and pinmux
  83             interface PeripheralSideUART uart;
  84             interface PeripheralSideGPIOA gpioa;
  85             interface PeripheralSideTWI twi;
  86       endinterface
  87
  88
  89    interface Ifc_pinmux;
  90       // this interface controls how each IO cell is routed.  setting
  91       // any given IO cell's mux control value will result in redirection
  92       // of not just the input or output to different peripheral functions
  93       // but also the *direction* control - if appropriate - as well.
  94       interface MuxSelectionLines mux_lines;
  95
  96       // this interface contains the inputs, outputs and direction-control
  97       // lines for all peripherals.  GPIO is considered to also be just
  98       // a peripheral because it also has in, out and direction-control.
  99       interface PeripheralSide peripheral_side;
 100
 101       // this interface is to be linked to the individual IO cells.
 102       // if looking at a "non-muxed" GPIO design, basically the
 103       // IO cell input, output and direction-control wires are cut
 104       // (giving six pairs of dangling wires, named left and right)
 105       // these iocells are routed in their place on one side ("left")
 106       // and the matching *GPIO* peripheral interfaces in/out/dir
 107       // connect to the OTHER side ("right").  the result is that
 108       // the muxer settings end up controlling the routing of where
 109       // the I/O from the IOcell actually goes.
 110       interface IOCellSide iocell_side;
 111    endinterface
 112    (*synthesize*)
 113    module mkpinmux(Ifc_pinmux);
 114
 115       // the followins wires capture the pin-mux selection
 116       // values for each mux assigned to a CELL
 117
 118       Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
 119       Wire#(Bit#(2)) wrcell1_mux<-mkDWire(0);
 120       Wire#(Bit#(2)) wrcell2_mux<-mkDWire(0);
 121       // following wires capture signals to IO CELL if io-0 is
 122       // allotted to it
 123       Wire#(Bit#(1)) cell0_mux_out<-mkDWire(0);
 124       Wire#(Bit#(1)) cell0_mux_outen<-mkDWire(0);
 125       Wire#(Bit#(1)) cell0_mux_in<-mkDWire(0);
 126
 127       // following wires capture signals to IO CELL if io-1 is
 128       // allotted to it
 129       Wire#(Bit#(1)) cell1_mux_out<-mkDWire(0);
 130       Wire#(Bit#(1)) cell1_mux_outen<-mkDWire(0);
 131       Wire#(Bit#(1)) cell1_mux_in<-mkDWire(0);
 132
 133       // following wires capture signals to IO CELL if io-2 is
 134       // allotted to it
 135       Wire#(Bit#(1)) cell2_mux_out<-mkDWire(0);
 136       Wire#(Bit#(1)) cell2_mux_outen<-mkDWire(0);
 137       Wire#(Bit#(1)) cell2_mux_in<-mkDWire(0);
 138
 139       // following wires capture signals to IO CELL if uart-0 is
 140       // allotted to it
 141       Wire#(Bit#(1)) wruart_tx<-mkDWire(0);
 142       Wire#(Bit#(1)) wruart_rx<-mkDWire(0);
 143
 144       // following wires capture signals to IO CELL if gpioa-0 is
 145       // allotted to it
 146       Wire#(Bit#(1)) wrgpioa_a0_out<-mkDWire(0);
 147       Wire#(Bit#(1)) wrgpioa_a0_outen<-mkDWire(0);
 148       Wire#(Bit#(1)) wrgpioa_a0_in<-mkDWire(0);
 149       Wire#(Bit#(1)) wrgpioa_a1_out<-mkDWire(0);
 150       Wire#(Bit#(1)) wrgpioa_a1_outen<-mkDWire(0);
 151       Wire#(Bit#(1)) wrgpioa_a1_in<-mkDWire(0);
 152       Wire#(Bit#(1)) wrgpioa_a2_out<-mkDWire(0);
 153       Wire#(Bit#(1)) wrgpioa_a2_outen<-mkDWire(0);
 154       Wire#(Bit#(1)) wrgpioa_a2_in<-mkDWire(0);
 155
 156       // following wires capture signals to IO CELL if twi-0 is
 157       // allotted to it
 158       Wire#(Bit#(1)) wrtwi_sda_out<-mkDWire(0);
 159       Wire#(Bit#(1)) wrtwi_sda_outen<-mkDWire(0);
 160       Wire#(Bit#(1)) wrtwi_sda_in<-mkDWire(0);
 161       Wire#(Bit#(1)) wrtwi_scl_out<-mkDWire(0);
 162       Wire#(Bit#(1)) wrtwi_scl_outen<-mkDWire(0);
 163       Wire#(Bit#(1)) wrtwi_scl_in<-mkDWire(0);
 164
 165
 166       /*====== This where the muxing starts for each io-cell======*/
 167       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 168        // output muxer for cell idx 0
 169       cell0_mux_out=
 170                         wrcell0_mux==0?wrgpioa_a0_out:
 171                         wrcell0_mux==1?wruart_tx:
 172                         wrcell0_mux==2?val0: // unused
 173                         wrtwi_sda_out;
 174
 175       // outen muxer for cell idx 0
 176       cell0_mux_outen=
 177                         wrcell0_mux==0?wrgpioa_a0_outen: // bi-directional
 178                         wrcell0_mux==1?wrgpioa_a0_outen: // uart_tx is an output
 179                         wrcell0_mux==2?val0: // unused
 180                         wrtwi_sda_outen; // bi-directional
 181
 182       // priority-in-muxer for cell idx 0
 183       rule assign_wrgpioa_a0_in_on_cell0(wrcell0_mux==0);
 184         wrgpioa_a0_in<=cell0_mux_in;
 185       endrule
 186
 187       rule assign_wrtwi_sda_in_on_cell0(wrcell0_mux==3);
 188         wrtwi_sda_in<=cell0_mux_in;
 189       endrule
 190
 191       // output muxer for cell idx 1
 192       cell1_mux_out=
 193                         wrcell1_mux==0?wrgpioa_a1_out:
 194                         wrcell1_mux==1?val0: // uart_rx is an input
 195                         wrcell1_mux==2?wrtwi_sda_out:
 196                         val0; // unused
 197
 198       // outen muxer for cell idx 1
 199       cell1_mux_outen=
 200                         wrcell1_mux==0?wrgpioa_a1_outen: // bi-directional
 201                         wrcell1_mux==1?val0: // uart_rx is an input
 202                         wrcell1_mux==2?wrtwi_sda_outen: // bi-directional
 203                         val0; // unused
 204
 205       // priority-in-muxer for cell idx 1
 206       rule assign_wrgpioa_a1_in_on_cell1(wrcell1_mux==0);
 207         wrgpioa_a1_in<=cell1_mux_in;
 208       endrule
 209
 210       rule assign_wruart_rx_on_cell1(wrcell1_mux==1);
 211         wruart_rx<=cell1_mux_in;
 212       endrule
 213
 214       rule assign_wrtwi_sda_in_on_cell1(wrcell1_mux==2);
 215         wrtwi_sda_in<=cell1_mux_in;
 216       endrule
 217
 218       // output muxer for cell idx 2
 219       cell2_mux_out=
 220                         wrcell2_mux==0?wrgpioa_a2_out:
 221                         wrcell2_mux==1?val0: // unused
 222                         wrcell2_mux==2?wrtwi_scl_out:
 223                         val0; // unused
 224
 225       // outen muxer for cell idx 2
 226       cell2_mux_outen=
 227                         wrcell2_mux==0?wrgpioa_a2_outen: // bi-directional
 228                         wrcell2_mux==1?val0: // unused
 229                         wrcell2_mux==2?wrtwi_scl_outen: // bi-directional
 230                         val0; // unused
 231
 232       // priority-in-muxer for cell idx 2
 233       rule assign_wrgpioa_a2_in_on_cell2(wrcell2_mux==0);
 234         wrgpioa_a2_in<=cell2_mux_in;
 235       endrule
 236
 237       rule assign_wrtwi_scl_in_on_cell2(wrcell2_mux==2);
 238         wrtwi_scl_in<=cell2_mux_in;
 239       endrule
 240
 241
 242       /*=========================================*/
 243       // dedicated cells
 244
 245
 246       /*============================================================*/
 247
 248     interface mux_lines = interface MuxSelectionLines
 249
 250       method Action  cell0_mux(Bit#(2) in);
 251          wrcell0_mux<=in;
 252       endmethod
 253
 254       method Action  cell1_mux(Bit#(2) in);
 255          wrcell1_mux<=in;
 256       endmethod
 257
 258       method Action  cell2_mux(Bit#(2) in);
 259          wrcell2_mux<=in;
 260       endmethod
 261
 262     endinterface;
 263
 264     interface iocell_side = interface IOCellSide
 265
 266       method io0_cell_out=cell0_mux_out;
 267       method io0_cell_outen=cell0_mux_outen;
 268       method Action  io0_cell_in(Bit#(1) in);
 269          cell0_mux_in<=in;
 270       endmethod
 271
 272       method io1_cell_out=cell1_mux_out;
 273       method io1_cell_outen=cell1_mux_outen;
 274       method Action  io1_cell_in(Bit#(1) in);
 275          cell1_mux_in<=in;
 276       endmethod
 277
 278       method io2_cell_out=cell2_mux_out;
 279       method io2_cell_outen=cell2_mux_outen;
 280       method Action  io2_cell_in(Bit#(1) in);
 281          cell2_mux_in<=in;
 282       endmethod
 283
 284      endinterface;
 285
 286     interface peripheral_side_uart = interface PeripheralSideUART
 287
 288       method Action  tx(Bit#(1) in);
 289          wruart_tx<=in;
 290       endmethod
 291       method rx=wruart_rx;
 292      endinterface
 293
 294     interface peripheral_side_gpioa = interface PeripheralSideGPIOA
 295
 296       method Action  a0_out(Bit#(1) in);
 297          wrgpioa_a0_out<=in;
 298       endmethod
 299       method Action  a0_outen(Bit#(1) in);
 300          wrgpioa_a0_outen<=in;
 301       endmethod
 302       method a0_in=wrgpioa_a0_in;
 303       method Action  a1_out(Bit#(1) in);
 304          wrgpioa_a1_out<=in;
 305       endmethod
 306       method Action  a1_outen(Bit#(1) in);
 307          wrgpioa_a1_outen<=in;
 308       endmethod
 309       method a1_in=wrgpioa_a1_in;
 310       method Action  a2_out(Bit#(1) in);
 311          wrgpioa_a2_out<=in;
 312       endmethod
 313       method Action  a2_outen(Bit#(1) in);
 314          wrgpioa_a2_outen<=in;
 315       endmethod
 316       method a2_in=wrgpioa_a2_in;
 317     endinterface
 318
 319     interface peripheral_side_twi = interface PeripheralSideTWI
 320
 321       method Action  sda_out(Bit#(1) in);
 322          wrtwi_sda_out<=in;
 323       endmethod
 324       method Action  sda_outen(Bit#(1) in);
 325          wrtwi_sda_outen<=in;
 326       endmethod
 327       method sda_in=wrtwi_sda_in;
 328       method Action  scl_out(Bit#(1) in);
 329          wrtwi_scl_out<=in;
 330       endmethod
 331       method Action  scl_outen(Bit#(1) in);
 332          wrtwi_scl_outen<=in;
 333       endmethod
 334       method scl_in=wrtwi_scl_in;
 335
 336      endinterface;
 337
 338     interface peripheral_side = interface PeripheralSide
 339
 340       interface uart = uart.mkuart();
 341       interface gpioa = gpioa.mkgpioa();
 342       interface twi = twi.mktwi();
 343
 344      endinterface;
 345    endmodule
 346 endpackage