src/test_bsv/pinmux_experiment.bsv

   1
   2 /*
   3    This BSV file has been generated by the PinMux tool available at:
   4    https://bitbucket.org/casl/pinmux.
   5
   6    Authors: Neel Gala, Luke
   7    Date of generation: Sun Jul 22 05:31:10 2018
   8 */
   9
  10 package pinmux;
  11
  12    interface MuxSelectionLines;
  13
  14       // declare the method which will capture the user pin-mux
  15       // selection values.The width of the input is dependent on the number
  16       // of muxes happening per IO. For now we have a generalized width
  17       // where each IO will have the same number of muxes.
  18      method  Action cell0_mux (Bit#(2) in);
  19      method  Action cell1_mux (Bit#(2) in);
  20      method  Action cell2_mux (Bit#(2) in);
  21       endinterface
  22
  23
  24       interface IOCellSide;
  25       // declare the interface to the IO cells.
  26       // Each IO cell will have 1 input field (output from pin mux)
  27       // and an output and out-enable field (input to pinmux)
  28           // interface declaration between IO-0 and pinmux
  29     (*always_ready,always_enabled*) method  Bit#(1) io0_cell_out;
  30     (*always_ready,always_enabled*) method  Bit#(1) io0_cell_outen;
  31     (*always_ready,always_enabled,result="io"*) method
  32                        Action io0_cell_in (Bit#(1) in);
  33           // interface declaration between IO-1 and pinmux
  34     (*always_ready,always_enabled*) method  Bit#(1) io1_cell_out;
  35     (*always_ready,always_enabled*) method  Bit#(1) io1_cell_outen;
  36     (*always_ready,always_enabled,result="io"*) method
  37                        Action io1_cell_in (Bit#(1) in);
  38           // interface declaration between IO-2 and pinmux
  39     (*always_ready,always_enabled*) method  Bit#(1) io2_cell_out;
  40     (*always_ready,always_enabled*) method  Bit#(1) io2_cell_outen;
  41     (*always_ready,always_enabled,result="io"*) method
  42                        Action io2_cell_in (Bit#(1) in);
  43       endinterface
  44
  45
  46       interface PeripheralSideUART;
  47           // interface declaration between UART and pinmux
  48     (*always_ready,always_enabled*) method  Action tx (Bit#(1) in);
  49     (*always_ready,always_enabled*) method  Bit#(1) rx;
  50       endinterface
  51
  52       interface PeripheralSideGPIOA;
  53           // interface declaration between GPIOA-0 and pinmux
  54     (*always_ready,always_enabled*) method  Action a0_out (Bit#(1) in);
  55     (*always_ready,always_enabled*) method  Action a0_outen (Bit#(1) in);
  56     (*always_ready,always_enabled*) method  Bit#(1) a0_in;
  57     (*always_ready,always_enabled*) method  Action a1_out (Bit#(1) in);
  58     (*always_ready,always_enabled*) method  Action a1_outen (Bit#(1) in);
  59     (*always_ready,always_enabled*) method  Bit#(1) a1_in;
  60     (*always_ready,always_enabled*) method  Action a2_out (Bit#(1) in);
  61     (*always_ready,always_enabled*) method  Action a2_outen (Bit#(1) in);
  62     (*always_ready,always_enabled*) method  Bit#(1) a2_in;
  63         endinterface
  64
  65       interface PeripheralSideTWI;
  66           // interface declaration between TWI and pinmux
  67     (*always_ready,always_enabled*) method  Action sda_out (Bit#(1) in);
  68     (*always_ready,always_enabled*) method  Action sda_outen (Bit#(1) in);
  69     (*always_ready,always_enabled*) method  Bit#(1) sda_in;
  70     (*always_ready,always_enabled*) method  Action scl_out (Bit#(1) in);
  71     (*always_ready,always_enabled*) method  Action scl_outen (Bit#(1) in);
  72     (*always_ready,always_enabled*) method  Bit#(1) scl_in;
  73       endinterface
  74
  75       interface PeripheralSide;
  76       // declare the interface to the peripherals
  77       // Each peripheral's function will be either an input, output
  78       // or be bi-directional.  an input field will be an output from the
  79       // peripheral and an output field will be an input to the peripheral.
  80       // Bi-directional functions also have an output-enable (which
  81       // again comes *in* from the peripheral)
  82           // interface declaration between UART-0 and pinmux
  83             interface PeripheralSideUART uart;
  84             interface PeripheralSideGPIOA gpioa;
  85             interface PeripheralSideTWI twi;
  86       endinterface
  87
  88
  89    interface Ifc_pinmux;
  90       // this interface controls how each IO cell is routed.  setting
  91       // any given IO cell's mux control value will result in redirection
  92       // of not just the input or output to different peripheral functions
  93       // but also the *direction* control - if appropriate - as well.
  94       interface MuxSelectionLines mux_lines;
  95
  96       // this interface contains the inputs, outputs and direction-control
  97       // lines for all peripherals.  GPIO is considered to also be just
  98       // a peripheral because it also has in, out and direction-control.
  99       interface PeripheralSide peripheral_side;
 100
 101       // this interface is to be linked to the individual IO cells.
 102       // if looking at a "non-muxed" GPIO design, basically the
 103       // IO cell input, output and direction-control wires are cut
 104       // (giving six pairs of dangling wires, named left and right)
 105       // these iocells are routed in their place on one side ("left")
 106       // and the matching *GPIO* peripheral interfaces in/out/dir
 107       // connect to the OTHER side ("right").  the result is that
 108       // the muxer settings end up controlling the routing of where
 109       // the I/O from the IOcell actually goes.
 110       interface IOCellSide iocell_side;
 111    endinterface
 112    (*synthesize*)
 113
 114    module mkgpioa(PeripheralSideGPIOA);
 115
 116       // allotted to it
 117       Wire#(Bit#(1)) wr_a0_out<-mkDWire(0);
 118       Wire#(Bit#(1)) wr_a0_outen<-mkDWire(0);
 119       Wire#(Bit#(1)) wr_a0_in<-mkDWire(0);
 120       Wire#(Bit#(1)) wr_a1_out<-mkDWire(0);
 121       Wire#(Bit#(1)) wr_a1_outen<-mkDWire(0);
 122       Wire#(Bit#(1)) wr_a1_in<-mkDWire(0);
 123       Wire#(Bit#(1)) wr_a2_out<-mkDWire(0);
 124       Wire#(Bit#(1)) wr_a2_outen<-mkDWire(0);
 125       Wire#(Bit#(1)) wr_a2_in<-mkDWire(0);
 126
 127     interface out = interface PeripheralSideGPIOA
 128
 129       method Action  a0_out(Bit#(1) in);
 130          wr_a0_out<=in;
 131       endmethod
 132       method Action  a0_outen(Bit#(1) in);
 133          wr_a0_outen<=in;
 134       endmethod
 135       method a0_in=wr_a0_in;
 136       method Action  a1_out(Bit#(1) in);
 137          wr_a1_out<=in;
 138       endmethod
 139       method Action  a1_outen(Bit#(1) in);
 140          wr_a1_outen<=in;
 141       endmethod
 142       method a1_in=wr_a1_in;
 143       method Action  a2_out(Bit#(1) in);
 144          wr_a2_out<=in;
 145       endmethod
 146       method Action  a2_outen(Bit#(1) in);
 147          wr_a2_outen<=in;
 148       endmethod
 149       method a2_in=wr_a2_in;
 150     endinterface
 151
 152    endmodule
 153
 154    module mkuart(PeripheralSideUART);
 155
 156       Wire#(Bit#(1)) wr_tx<-mkDWire(0);
 157       Wire#(Bit#(1)) wr_rx<-mkDWire(0);
 158
 159     interface out = interface PeripheralSideUART
 160
 161       method Action  tx(Bit#(1) in);
 162          wr_tx<=in;
 163       endmethod
 164       method rx=wr_rx;
 165      endinterface
 166
 167    endmodule
 168
 169
 170    module mktwi(PeripheralSideTWI);
 171
 172       // following wires capture signals to IO CELL if twi-0 is
 173       // allotted to it
 174       Wire#(Bit#(1)) wr_sda_out<-mkDWire(0);
 175       Wire#(Bit#(1)) wr_sda_outen<-mkDWire(0);
 176       Wire#(Bit#(1)) wr_sda_in<-mkDWire(0);
 177       Wire#(Bit#(1)) wr_scl_out<-mkDWire(0);
 178       Wire#(Bit#(1)) wr_scl_outen<-mkDWire(0);
 179       Wire#(Bit#(1)) wr_scl_in<-mkDWire(0);
 180
 181
 182     interface out = interface PeripheralSideTWI
 183
 184       method Action  sda_out(Bit#(1) in);
 185          wr_sda_out<=in;
 186       endmethod
 187       method Action  sda_outen(Bit#(1) in);
 188          wr_sda_outen<=in;
 189       endmethod
 190       method sda_in=wr_sda_in;
 191       method Action  scl_out(Bit#(1) in);
 192          wr_scl_out<=in;
 193       endmethod
 194       method Action  scl_outen(Bit#(1) in);
 195          wr_scl_outen<=in;
 196       endmethod
 197       method scl_in=wr_scl_in;
 198
 199      endinterface;
 200
 201    endmodule
 202
 203
 204    module mkperipherals(PeripheralSide);
 205
 206       PeripheralSideUART uart = uart.mkuart();
 207       PeripheralSideGPIOA gpioa = gpioa.mkgpioa();
 208       PeripheralSideTWI twi = twi.mktwi();
 209
 210     interface out = interface PeripheralSide
 211
 212       interface uart = uart.out;
 213       interface gpioa = gpioa.out;
 214       interface twi = twi.out;
 215
 216      endinterface;
 217
 218    endmodule
 219
 220    module mkpinmux(Ifc_pinmux);
 221
 222       PeripheralSide peripherals = mkperipherals();
 223
 224       // the followins wires capture the pin-mux selection
 225       // values for each mux assigned to a CELL
 226
 227       Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
 228       Wire#(Bit#(2)) wrcell1_mux<-mkDWire(0);
 229       Wire#(Bit#(2)) wrcell2_mux<-mkDWire(0);
 230       // following wires capture signals to IO CELL if io-0 is
 231       // allotted to it
 232       Wire#(Bit#(1)) cell0_mux_out<-mkDWire(0);
 233       Wire#(Bit#(1)) cell0_mux_outen<-mkDWire(0);
 234       Wire#(Bit#(1)) cell0_mux_in<-mkDWire(0);
 235
 236       // following wires capture signals to IO CELL if io-1 is
 237       // allotted to it
 238       Wire#(Bit#(1)) cell1_mux_out<-mkDWire(0);
 239       Wire#(Bit#(1)) cell1_mux_outen<-mkDWire(0);
 240       Wire#(Bit#(1)) cell1_mux_in<-mkDWire(0);
 241
 242       // following wires capture signals to IO CELL if io-2 is
 243       // allotted to it
 244       Wire#(Bit#(1)) cell2_mux_out<-mkDWire(0);
 245       Wire#(Bit#(1)) cell2_mux_outen<-mkDWire(0);
 246       Wire#(Bit#(1)) cell2_mux_in<-mkDWire(0);
 247
 248       // following wires capture signals to IO CELL if uart-0 is
 249       // allotted to it
 250       Wire#(Bit#(1)) wruart_tx<-mkDWire(0);
 251       Wire#(Bit#(1)) wruart_rx<-mkDWire(0);
 252
 253       // following wires capture signals to IO CELL if gpioa-0 is
 254       // allotted to it
 255       Wire#(Bit#(1)) wrgpioa_a0_out<-mkDWire(0);
 256       Wire#(Bit#(1)) wrgpioa_a0_outen<-mkDWire(0);
 257       Wire#(Bit#(1)) wrgpioa_a0_in<-mkDWire(0);
 258       Wire#(Bit#(1)) wrgpioa_a1_out<-mkDWire(0);
 259       Wire#(Bit#(1)) wrgpioa_a1_outen<-mkDWire(0);
 260       Wire#(Bit#(1)) wrgpioa_a1_in<-mkDWire(0);
 261       Wire#(Bit#(1)) wrgpioa_a2_out<-mkDWire(0);
 262       Wire#(Bit#(1)) wrgpioa_a2_outen<-mkDWire(0);
 263       Wire#(Bit#(1)) wrgpioa_a2_in<-mkDWire(0);
 264
 265       // following wires capture signals to IO CELL if twi-0 is
 266       // allotted to it
 267       Wire#(Bit#(1)) wrtwi_sda_out<-mkDWire(0);
 268       Wire#(Bit#(1)) wrtwi_sda_outen<-mkDWire(0);
 269       Wire#(Bit#(1)) wrtwi_sda_in<-mkDWire(0);
 270       Wire#(Bit#(1)) wrtwi_scl_out<-mkDWire(0);
 271       Wire#(Bit#(1)) wrtwi_scl_outen<-mkDWire(0);
 272       Wire#(Bit#(1)) wrtwi_scl_in<-mkDWire(0);
 273
 274
 275       /*====== This where the muxing starts for each io-cell======*/
 276       Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 277        // output muxer for cell idx 0
 278       cell0_mux_out=
 279                         wrcell0_mux==0?wrgpioa_a0_out:
 280                         wrcell0_mux==1?wruart_tx:
 281                         wrcell0_mux==2?val0: // unused
 282                         wrtwi_sda_out;
 283
 284       // outen muxer for cell idx 0
 285       cell0_mux_outen=
 286                         wrcell0_mux==0?wrgpioa_a0_outen: // bi-directional
 287                         wrcell0_mux==1?wrgpioa_a0_outen: // uart_tx is an output
 288                         wrcell0_mux==2?val0: // unused
 289                         wrtwi_sda_outen; // bi-directional
 290
 291       // priority-in-muxer for cell idx 0
 292       rule assign_wrgpioa_a0_in_on_cell0(wrcell0_mux==0);
 293         wrgpioa_a0_in<=cell0_mux_in;
 294       endrule
 295
 296       rule assign_wrtwi_sda_in_on_cell0(wrcell0_mux==3);
 297         wrtwi_sda_in<=cell0_mux_in;
 298       endrule
 299
 300       // output muxer for cell idx 1
 301       cell1_mux_out=
 302                         wrcell1_mux==0?wrgpioa_a1_out:
 303                         wrcell1_mux==1?val0: // uart_rx is an input
 304                         wrcell1_mux==2?wrtwi_sda_out:
 305                         val0; // unused
 306
 307       // outen muxer for cell idx 1
 308       cell1_mux_outen=
 309                         wrcell1_mux==0?wrgpioa_a1_outen: // bi-directional
 310                         wrcell1_mux==1?val0: // uart_rx is an input
 311                         wrcell1_mux==2?wrtwi_sda_outen: // bi-directional
 312                         val0; // unused
 313
 314       // priority-in-muxer for cell idx 1
 315       rule assign_wrgpioa_a1_in_on_cell1(wrcell1_mux==0);
 316         wrgpioa_a1_in<=cell1_mux_in;
 317       endrule
 318
 319       rule assign_wruart_rx_on_cell1(wrcell1_mux==1);
 320         wruart_rx<=cell1_mux_in;
 321       endrule
 322
 323       rule assign_wrtwi_sda_in_on_cell1(wrcell1_mux==2);
 324         wrtwi_sda_in<=cell1_mux_in;
 325       endrule
 326
 327       // output muxer for cell idx 2
 328       cell2_mux_out=
 329                         wrcell2_mux==0?wrgpioa_a2_out:
 330                         wrcell2_mux==1?val0: // unused
 331                         wrcell2_mux==2?wrtwi_scl_out:
 332                         val0; // unused
 333
 334       // outen muxer for cell idx 2
 335       cell2_mux_outen=
 336                         wrcell2_mux==0?wrgpioa_a2_outen: // bi-directional
 337                         wrcell2_mux==1?val0: // unused
 338                         wrcell2_mux==2?wrtwi_scl_outen: // bi-directional
 339                         val0; // unused
 340
 341       // priority-in-muxer for cell idx 2
 342       rule assign_wrgpioa_a2_in_on_cell2(wrcell2_mux==0);
 343         wrgpioa_a2_in<=cell2_mux_in;
 344       endrule
 345
 346       rule assign_wrtwi_scl_in_on_cell2(wrcell2_mux==2);
 347         wrtwi_scl_in<=cell2_mux_in;
 348       endrule
 349
 350
 351       /*=========================================*/
 352       // dedicated cells
 353
 354
 355       /*============================================================*/
 356
 357     interface mux_lines = interface MuxSelectionLines
 358
 359       method Action  cell0_mux(Bit#(2) in);
 360          wrcell0_mux<=in;
 361       endmethod
 362
 363       method Action  cell1_mux(Bit#(2) in);
 364          wrcell1_mux<=in;
 365       endmethod
 366
 367       method Action  cell2_mux(Bit#(2) in);
 368          wrcell2_mux<=in;
 369       endmethod
 370
 371     endinterface;
 372
 373     interface iocell_side = interface IOCellSide
 374
 375       method io0_cell_out=cell0_mux_out;
 376       method io0_cell_outen=cell0_mux_outen;
 377       method Action  io0_cell_in(Bit#(1) in);
 378          cell0_mux_in<=in;
 379       endmethod
 380
 381       method io1_cell_out=cell1_mux_out;
 382       method io1_cell_outen=cell1_mux_outen;
 383       method Action  io1_cell_in(Bit#(1) in);
 384          cell1_mux_in<=in;
 385       endmethod
 386
 387       method io2_cell_out=cell2_mux_out;
 388       method io2_cell_outen=cell2_mux_outen;
 389       method Action  io2_cell_in(Bit#(1) in);
 390          cell2_mux_in<=in;
 391       endmethod
 392
 393      endinterface;
 394
 395     interface peripheral_side = interface PeripheralSide
 396
 397       interface uart = peripherals.uart.out;
 398       interface gpioa = peripherals.gpioa.out;
 399       interface twi = peripherals.twi.out;
 400
 401      endinterface;
 402    endmodule
 403 endpackage