src/test_bsv/tests/test_pinmux.py

   1 # Simple tests for an pinmux module
   2 import cocotb
   3 from cocotb.triggers import Timer
   4 from cocotb.result import TestFailure
   5 #from pinmux_model import pinmux_model
   6 import random
   7
   8
   9 """ dut is design under test """
  10
  11
  12 @cocotb.test()
  13 def pinmux_basic_test(dut):
  14     """Test for 5 + 10"""
  15     yield Timer(2)
  16     # mux selection lines, each input two bit wide
  17     dut.mux_lines_cell0_mux_in = 1
  18     dut.mux_lines_cell1_mux_in = 2
  19     dut.mux_lines_cell2_mux_in = 0
  20     yield Timer(2)
  21     # enable input for mux
  22     dut.EN_mux_lines_cell0_mux = 1
  23     dut.EN_mux_lines_cell1_mux = 1
  24     dut.EN_mux_lines_cell2_mux = 1
  25
  26     yield Timer(2)
  27
  28     # GPIO2-out test
  29     # GPIO is inout peripheral
  30     dut.peripheral_side_gpioa_a2_out_in = 0
  31     dut.peripheral_side_gpioa_a2_outen_in = 1
  32
  33     yield Timer(2)
  34
  35     if dut.iocell_side_io2_cell_out != 0:  # output of iopad
  36         raise TestFailure(
  37             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 0" %
  38             str(dut.iocell_side_io2_cell_out))
  39
  40     dut.peripheral_side_gpioa_a2_out_in = 1
  41
  42     yield Timer(2)
  43
  44     if dut.iocell_side_io2_cell_out != 1:
  45         raise TestFailure(
  46             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" %
  47             str(dut.iocell_side_io2_cell_out))
  48
  49     # GPIO2-in test (first see if it's tri-state)
  50     if str(dut.peripheral_side_gpioa_a2_in) != "x":
  51         raise TestFailure(
  52             "gpioa_a2=0/mux=0/out=1 %s gpio_a2_in != x" %
  53             str(dut.peripheral_side_gpioa_a2_in))
  54
  55     dut.peripheral_side_gpioa_a2_outen_in = 0
  56     dut.iocell_side_io2_cell_in_in = 0
  57     yield Timer(2)
  58
  59     if dut.peripheral_side_gpioa_a2_in != 0:
  60         raise TestFailure(
  61             "iocell_io2=0/mux=0/out=0 %s gpioa_a2 != 0" %
  62             str(dut.peripheral_side_gpioa_a2_in))
  63
  64     dut.iocell_side_io2_cell_in_in = 1
  65     yield Timer(2)
  66
  67     if dut.peripheral_side_gpioa_a2_in != 1:
  68         raise TestFailure(
  69             "iocell_io2=1/mux=0/out=0 %s gpioa_a2 != 1" %
  70             str(dut.peripheral_side_gpioa_a2_in))
  71
  72     dut.peripheral_side_gpioa_a2_outen_in = 1
  73     dut.iocell_side_io2_cell_in_in = 0
  74     yield Timer(2)
  75     dut._log.info("gpioa_a2_in %s" % dut.peripheral_side_gpioa_a2_in)
  76
  77     if dut.iocell_side_io2_cell_out != 1:
  78         raise TestFailure(
  79             "gpioa_a2=0/mux=0/out=1 %s iocell_io2 != 1" %
  80             str(dut.iocell_side_io2_cell_out))
  81
  82     # UART
  83     yield Timer(2)
  84     dut.peripheral_side_uart_tx_in = 1
  85     dut.peripheral_side_gpioa_a0_outen_in = 1
  86
  87     yield Timer(2)
  88
  89     if dut.iocell_side_io0_cell_out != 1:
  90         raise TestFailure(
  91             "uart_tx=1/mux=0/out=1 %s iocell_io0 != 1" %
  92             str(dut.iocell_side_io0_cell_out))
  93
  94     dut.peripheral_side_uart_tx_in = 0
  95
  96     yield Timer(2)
  97
  98     if dut.iocell_side_io0_cell_out != 0:
  99         raise TestFailure(
 100             "uart_tx=0/mux=0/out=1 %s iocell_io0 != 0" %
 101             str(dut.iocell_side_io0_cell_out))
 102
 103     # TWI
 104     yield Timer(2)
 105     # define input variables
 106     dut.peripheral_side_twi_sda_out_in = 0
 107     dut.peripheral_side_twi_sda_outen_in = 1
 108
 109     yield Timer(2)
 110
 111     dut._log.info("io1_out %s" % dut.iocell_side_io1_cell_out)
 112     # Test for out for twi_sda
 113     if dut.iocell_side_io1_cell_out != 0:
 114         raise TestFailure(
 115             "twi_sda=0/mux=0/out=1 %s iocell_io1 != 0" %
 116             str(dut.iocell_side_io1_cell_out))
 117
 118     dut.peripheral_side_twi_sda_out_in = 1
 119     yield Timer(2)
 120
 121     if dut.iocell_side_io1_cell_out != 1:
 122         raise TestFailure(
 123             "twi_sda=1/mux=0/out=1 %s iocell_io1 != 1" %
 124             str(dut.iocell_side_io1_cell_out))
 125
 126     # Test for in
 127     # first check for tristate
 128     if str(dut.peripheral_side_twi_sda_in) != "x":
 129         raise TestFailure(
 130             "twi_sda=0/mux=0/out=1 %s twi_sda_in != x" %
 131             str(dut.peripheral_side_twi_sda_in))
 132
 133     dut.peripheral_side_twi_sda_outen_in = 0
 134     dut.iocell_side_io1_cell_in_in = 0
 135     yield Timer(2)
 136
 137     if dut.peripheral_side_twi_sda_in != 0:
 138         raise TestFailure(
 139             "iocell_io1=0/mux=0/out=0 %s twi_sda != 0" %
 140             str(dut.peripheral_side_twi_sda_in))
 141
 142     dut.iocell_side_io1_cell_in_in = 1
 143     yield Timer(2)
 144
 145     if dut.peripheral_side_twi_sda_in != 1:
 146         raise TestFailure(
 147             "iocell_io1=0/mux=0/out=0 %s twi_sda != 0" %
 148             str(dut.peripheral_side_twi_sda_in))
 149
 150     dut.peripheral_side_twi_sda_outen_in = 1
 151     dut.iocell_side_io1_cell_in_in = 0
 152     yield Timer(2)
 153     dut._log.info("twi_sda_in %s" % dut.peripheral_side_twi_sda_in)
 154
 155     if dut.iocell_side_io1_cell_out != 1:
 156         raise TestFailure(
 157             "twi_sda=0/mux=0/out=1 %s iocell_io1 != 1" %
 158             str(dut.iocell_side_io1_cell_out))
 159
 160     yield Timer(2)
 161
 162     # Test for out for twi_scl
 163     dut.peripheral_side_twi_scl_out_in = 0
 164     dut.peripheral_side_twi_scl_outen_in = 1
 165     yield Timer(2)
 166
 167     if dut.iocell_side_io2_cell_out != 0:
 168         raise TestFailure(
 169             "twi_scl=0/mux=0/out=1 %s iocell_io2 != 0" %
 170             str(dut.iocell_side_io2_cell_out))
 171
 172     dut.peripheral_side_twi_scl_out_in = 1
 173     yield Timer(2)
 174
 175     if dut.iocell_side_io2_cell_out != 1:
 176         raise TestFailure(
 177             "twi_scl=0/mux=0/out=1 %s iocell_io2 != 0" %
 178             str(dut.iocell_side_io2_cell_out))
 179
 180     # Test for in
 181     # first check for tristate
 182     if str(dut.peripheral_side_twi_scl_in) != "x":
 183         raise TestFailure(
 184             "twi_scl=0/mux=0/out=1 %s twi_scl_in != x" %
 185             str(dut.peripheral_side_twi_scl_in))
 186
 187     dut.peripheral_side_twi_scl_outen_in = 0
 188     dut.iocell_side_io2_cell_in_in = 0
 189     yield Timer(2)
 190
 191     if dut.peripheral_side_twi_scl_in != 0:
 192         raise TestFailure(
 193             "iocell_io2=0/mux=0/out=0 %s twi_scl != 0" %
 194             str(dut.peripheral_side_twi_scl_in))
 195
 196     dut.iocell_side_io2_cell_in_in = 1
 197     yield Timer(2)
 198
 199     if dut.peripheral_side_twi_scl_in != 1:
 200         raise TestFailure(
 201             "iocell_io2=1/mux=0/out=0 %s twi_scl != 1" %
 202             str(dut.peripheral_side_twi_scl_in))
 203
 204     dut.peripheral_side_twi_scl_outen_in = 1
 205     dut.iocell_side_io2_cell_in_in = 0
 206     yield Timer(2)
 207     dut._log.info("twi_scl_in %s" % dut.peripheral_side_twi_scl_in)
 208
 209     if dut.iocell_side_io2_cell_out != 1:
 210         raise TestFailure(
 211             "twi_scl=0/mux=0/out=1 %s iocell_io2 != 1" %
 212             str(dut.iocell_side_io2_cell_out))
 213
 214     yield Timer(2)
 215
 216     dut._log.info("Ok!")
 217
 218 @cocotb.test()
 219 def pinmux_randomised_test(dut):
 220     """Test for adding 2 random numbers multiple times"""
 221
 222     return
 223
 224     yield Timer(2)
 225
 226     for i in range(10):
 227         A = random.randint(0, 15)
 228         B = random.randint(0, 15)
 229
 230         dut.A = A
 231         dut.B = B
 232
 233         yield Timer(2)
 234
 235         if int(dut.X) != pinmux_model(A, B):
 236             raise TestFailure(
 237                 "Randomised test failed with: %s + %s = %s" %
 238                 (int(dut.A), int(dut.B), int(dut.X)))
 239         else:  # these last two lines are not strictly necessary
 240             dut._log.info("Ok!")