targets/de0nano.py

   1 from migen.fhdl.std import *
   2
   3 from misoclib.mem.sdram.module import IS42S16160
   4 from misoclib.mem.sdram.phy import gensdrphy
   5 from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
   6 from misoclib.soc.sdram import SDRAMSoC
   7
   8
   9 class _PLL(Module):
  10     def __init__(self, period_in, name, phase_shift, operation_mode):
  11         self.clk_in = Signal()
  12         self.clk_out = Signal()
  13
  14         self.specials += Instance("ALTPLL",
  15                                   p_bandwidth_type = "AUTO",
  16                                   p_clk0_divide_by = 1,
  17                                   p_clk0_duty_cycle = 50,
  18                                   p_clk0_multiply_by = 2,
  19                                   p_clk0_phase_shift = "{}".format(str(phase_shift)),
  20                                   p_compensate_clock = "CLK0",
  21                                   p_inclk0_input_frequency = int(period_in*1000),
  22                                   p_intended_device_family = "Cyclone IV E",
  23                                   p_lpm_hint = "CBX_MODULE_PREFIX={}_pll".format(name),
  24                                   p_lpm_type = "altpll",
  25                                   p_operation_mode = operation_mode,
  26                                   i_inclk=self.clk_in,
  27                                   o_clk=self.clk_out,
  28                                   i_areset=0,
  29                                   i_clkena=0x3f,
  30                                   i_clkswitch=0,
  31                                   i_configupdate=0,
  32                                   i_extclkena=0xf,
  33                                   i_fbin=1,
  34                                   i_pfdena=1,
  35                                   i_phasecounterselect=0xf,
  36                                   i_phasestep=1,
  37                                   i_phaseupdown=1,
  38                                   i_pllena=1,
  39                                   i_scanaclr=0,
  40                                   i_scanclk=0,
  41                                   i_scanclkena=1,
  42                                   i_scandata=0,
  43                                   i_scanread=0,
  44                                   i_scanwrite=0
  45         )
  46
  47
  48 class _CRG(Module):
  49     def __init__(self, platform):
  50         self.clock_domains.cd_sys = ClockDomain()
  51         self.clock_domains.cd_sys_ps = ClockDomain()
  52         self.clock_domains.cd_por = ClockDomain(reset_less=True)
  53
  54         clk50 = platform.request("clk50")
  55
  56         sys_pll = _PLL(20, "sys", 0, "NORMAL")
  57         self.submodules += sys_pll
  58         self.comb += [
  59             sys_pll.clk_in.eq(clk50),
  60             self.cd_sys.clk.eq(sys_pll.clk_out)
  61         ]
  62
  63         sdram_pll = _PLL(20, "sdram", -3000, "ZERO_DELAY_BUFFER")
  64         self.submodules += sdram_pll
  65         self.comb += [
  66             sdram_pll.clk_in.eq(clk50),
  67             self.cd_sys_ps.clk.eq(sdram_pll.clk_out)
  68         ]
  69
  70         # Power on Reset (vendor agnostic)
  71         rst_n = Signal()
  72         self.sync.por += rst_n.eq(1)
  73         self.comb += [
  74             self.cd_por.clk.eq(self.cd_sys.clk),
  75             self.cd_sys.rst.eq(~rst_n),
  76             self.cd_sys_ps.rst.eq(~rst_n)
  77         ]
  78
  79         self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
  80
  81
  82 class BaseSoC(SDRAMSoC):
  83     default_platform = "de0nano"
  84
  85     def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
  86         SDRAMSoC.__init__(self, platform,
  87                           clk_freq=100*1000000,
  88                           integrated_rom_size=0x8000,
  89                           sdram_controller_settings=sdram_controller_settings,
  90                           **kwargs)
  91
  92         self.submodules.crg = _CRG(platform)
  93
  94         if not self.integrated_main_ram_size:
  95             self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"),
  96                                                          IS42S16160(self.clk_freq))
  97             self.register_sdram_phy(self.sdrphy)
  98
  99 default_subtarget = BaseSoC