targets/kc705.py

   1 from migen.fhdl.std import *
   2 from migen.genlib.resetsync import AsyncResetSynchronizer
   3
   4 from misoclib import lasmicon, spiflash, ethmac
   5 from misoclib.sdramphy import k7ddrphy
   6 from misoclib.gensoc import SDRAMSoC
   7 from misoclib.ethmac.phys import gmii
   8
   9 class _CRG(Module):
  10         def __init__(self, platform):
  11                 self.clock_domains.cd_sys = ClockDomain()
  12                 self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
  13                 self.clock_domains.cd_clk200 = ClockDomain()
  14
  15                 clk200 = platform.request("clk200")
  16                 clk200_se = Signal()
  17                 self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
  18
  19                 pll_locked = Signal()
  20                 pll_fb = Signal()
  21                 pll_sys = Signal()
  22                 pll_sys4x = Signal()
  23                 pll_clk200 = Signal()
  24                 self.specials += [
  25                         Instance("PLLE2_BASE",
  26                                 p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
  27
  28                                 # VCO @ 1GHz
  29                                 p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
  30                                 p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
  31                                 i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
  32
  33                                 # 125MHz
  34                                 p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
  35
  36                                 # 500MHz
  37                                 p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_sys4x,
  38
  39                                 # 200MHz
  40                                 p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=pll_clk200,
  41
  42                                 p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
  43
  44                                 p_CLKOUT4_DIVIDE=4, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
  45                         ),
  46                         Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
  47                         Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
  48                         Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
  49                         AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
  50                         AsyncResetSynchronizer(self.cd_clk200, ~pll_locked),
  51                 ]
  52
  53                 reset_counter = Signal(4, reset=15)
  54                 ic_reset = Signal(reset=1)
  55                 self.sync.clk200 += \
  56                         If(reset_counter != 0,
  57                                 reset_counter.eq(reset_counter - 1)
  58                         ).Else(
  59                                 ic_reset.eq(0)
  60                         )
  61                 self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
  62
  63 class BaseSoC(SDRAMSoC):
  64         default_platform = "kc705"
  65
  66         csr_map = {
  67                 "ddrphy":       10,
  68         }
  69         csr_map.update(SDRAMSoC.csr_map)
  70
  71         def __init__(self, platform, **kwargs):
  72                 SDRAMSoC.__init__(self, platform,
  73                         clk_freq=125*1000000, cpu_reset_address=0xaf0000,
  74                         **kwargs)
  75
  76                 self.submodules.crg = _CRG(platform)
  77
  78                 sdram_geom = lasmicon.GeomSettings(
  79                         bank_a=3,
  80                         row_a=16,
  81                         col_a=10
  82                 )
  83                 sdram_timing = lasmicon.TimingSettings(
  84                         tRP=self.ns(15),
  85                         tRCD=self.ns(15),
  86                         tWR=self.ns(15),
  87                         tWTR=2,
  88                         tREFI=self.ns(7800, False),
  89                         tRFC=self.ns(70),
  90
  91                         req_queue_size=8,
  92                         read_time=32,
  93                         write_time=16
  94                 )
  95                 self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
  96                 self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing)
  97
  98                 # BIOS is in SPI flash
  99                 spiflash_pads = platform.request("spiflash")
 100                 spiflash_pads.clk = Signal()
 101                 self.specials += Instance("STARTUPE2",
 102                         i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
 103                         i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
 104                 self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
 105                 self.flash_boot_address = 0xb00000
 106                 self.register_rom(self.spiflash.bus)
 107
 108 class MiniSoC(BaseSoC):
 109         csr_map = {
 110                 "ethphy":               11,
 111                 "ethmac":               12,
 112         }
 113         csr_map.update(BaseSoC.csr_map)
 114
 115         interrupt_map = {
 116                 "ethmac":               2,
 117         }
 118         interrupt_map.update(BaseSoC.interrupt_map)
 119
 120         def __init__(self, platform, **kwargs):
 121                 BaseSoC.__init__(self, platform, **kwargs)
 122
 123                 self.submodules.ethphy = gmii.GMIIPHY(platform.request("eth_clocks"), platform.request("eth"))
 124                 self.submodules.ethmac = ethmac.EthMAC(phy=self.ethphy, with_hw_preamble_crc=True)
 125                 self.add_wb_slave(lambda a: a[26:29] == 3, self.ethmac.bus)
 126                 self.add_cpu_memory_region("ethmac_mem", 0xb0000000, 0x2000)
 127
 128 default_subtarget = BaseSoC