targets/kc705.py

   1 from migen.fhdl.std import *
   2 from migen.genlib.resetsync import AsyncResetSynchronizer
   3
   4 from misoclib.mem.sdram.module import MT8JTF12864
   5 from misoclib.mem.sdram.phy import k7ddrphy
   6 from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
   7 from misoclib.mem.flash import spiflash
   8 from misoclib.soc import mem_decoder
   9 from misoclib.soc.sdram import SDRAMSoC
  10
  11 from misoclib.com.liteeth.phy import LiteEthPHY
  12 from misoclib.com.liteeth.core.mac import LiteEthMAC
  13
  14
  15 class _CRG(Module):
  16     def __init__(self, platform):
  17         self.clock_domains.cd_sys = ClockDomain()
  18         self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
  19         self.clock_domains.cd_clk200 = ClockDomain()
  20
  21         clk200 = platform.request("clk200")
  22         clk200_se = Signal()
  23         self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
  24
  25         rst = platform.request("cpu_reset")
  26
  27         pll_locked = Signal()
  28         pll_fb = Signal()
  29         self.pll_sys = Signal()
  30         pll_sys4x = Signal()
  31         pll_clk200 = Signal()
  32         self.specials += [
  33             Instance("PLLE2_BASE",
  34                      p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
  35
  36                      # VCO @ 1GHz
  37                      p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
  38                      p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
  39                      i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
  40
  41                      # 125MHz
  42                      p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=self.pll_sys,
  43
  44                      # 500MHz
  45                      p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_sys4x,
  46
  47                      # 200MHz
  48                      p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=pll_clk200,
  49
  50                      p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
  51
  52                      p_CLKOUT4_DIVIDE=4, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
  53             ),
  54             Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
  55             Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
  56             Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
  57             AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst),
  58             AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst),
  59         ]
  60
  61         reset_counter = Signal(4, reset=15)
  62         ic_reset = Signal(reset=1)
  63         self.sync.clk200 += \
  64             If(reset_counter != 0,
  65                 reset_counter.eq(reset_counter - 1)
  66             ).Else(
  67                 ic_reset.eq(0)
  68             )
  69         self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
  70
  71
  72 class BaseSoC(SDRAMSoC):
  73     default_platform = "kc705"
  74
  75     csr_map = {
  76         "spiflash": 16,
  77         "ddrphy":   17,
  78     }
  79     csr_map.update(SDRAMSoC.csr_map)
  80
  81     def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
  82         SDRAMSoC.__init__(self, platform,
  83                           clk_freq=125*1000000, cpu_reset_address=0xaf0000,
  84                           sdram_controller_settings=sdram_controller_settings,
  85                           **kwargs)
  86
  87         self.submodules.crg = _CRG(platform)
  88
  89         if not self.integrated_main_ram_size:
  90             self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"),
  91                                                        MT8JTF12864(self.clk_freq))
  92             self.register_sdram_phy(self.ddrphy)
  93
  94         if not self.integrated_rom_size:
  95             spiflash_pads = platform.request("spiflash")
  96             spiflash_pads.clk = Signal()
  97             self.specials += Instance("STARTUPE2",
  98                                       i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
  99                                       i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
 100             self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
 101             self.add_constant("SPIFLASH_PAGE_SIZE", 256)
 102             self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
 103             self.flash_boot_address = 0xb00000
 104             self.register_rom(self.spiflash.bus)
 105
 106
 107 class MiniSoC(BaseSoC):
 108     csr_map = {
 109         "ethphy": 18,
 110         "ethmac": 19,
 111     }
 112     csr_map.update(BaseSoC.csr_map)
 113
 114     interrupt_map = {
 115         "ethmac": 2,
 116     }
 117     interrupt_map.update(BaseSoC.interrupt_map)
 118
 119     mem_map = {
 120         "ethmac": 0x30000000,  # (shadow @0xb0000000)
 121     }
 122     mem_map.update(BaseSoC.mem_map)
 123
 124     def __init__(self, platform, **kwargs):
 125         BaseSoC.__init__(self, platform, **kwargs)
 126
 127         self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=self.clk_freq)
 128         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
 129         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
 130         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 131
 132 default_subtarget = BaseSoC