targets/minispartan6.py

   1 from fractions import Fraction
   2
   3 from migen.fhdl.std import *
   4 from migen.genlib.resetsync import AsyncResetSynchronizer
   5
   6 from misoclib.mem.sdram.module import AS4C16M16
   7 from misoclib.mem.sdram.phy import gensdrphy
   8 from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
   9 from misoclib.soc.sdram import SDRAMSoC
  10
  11 class _CRG(Module):
  12     def __init__(self, platform, clk_freq):
  13         self.clock_domains.cd_sys = ClockDomain()
  14         self.clock_domains.cd_sys_ps = ClockDomain()
  15
  16         f0 = 32*1000000
  17         clk32 = platform.request("clk32")
  18         clk32a = Signal()
  19         self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
  20         clk32b = Signal()
  21         self.specials += Instance("BUFIO2", p_DIVIDE=1,
  22             p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
  23             i_I=clk32a, o_DIVCLK=clk32b)
  24         f = Fraction(int(clk_freq), int(f0))
  25         n, m, p = f.denominator, f.numerator, 8
  26         assert f0/n*m == clk_freq
  27         pll_lckd = Signal()
  28         pll_fb = Signal()
  29         pll = Signal(6)
  30         self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
  31             p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
  32             p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
  33             i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
  34             p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
  35             i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
  36             p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
  37             i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
  38             o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
  39             o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
  40             o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
  41             o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
  42             o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
  43             o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
  44             p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//1,
  45             p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
  46             p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
  47             p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
  48             p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
  49             p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
  50         )
  51         self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
  52         self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
  53         self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd)
  54
  55         self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
  56             p_INIT=0, p_SRTYPE="SYNC",
  57             i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
  58             i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
  59             o_Q=platform.request("sdram_clock"))
  60
  61 class BaseSoC(SDRAMSoC):
  62     default_platform = "minispartan6"
  63
  64     def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
  65         clk_freq = 80*1000000
  66         SDRAMSoC.__init__(self, platform, clk_freq,
  67             integrated_rom_size=0x8000,
  68             sdram_controller_settings=sdram_controller_settings,
  69             **kwargs)
  70
  71         self.submodules.crg = _CRG(platform, clk_freq)
  72
  73         if not self.integrated_main_ram_size:
  74             self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), AS4C16M16(clk_freq))
  75             self.register_sdram_phy(self.sdrphy)
  76
  77 default_subtarget = BaseSoC