2 from fractions
import Fraction
5 from migen
.fhdl
.std
import *
6 from mibuild
.generic_platform
import ConstraintError
8 from misoclib
.mem
.sdram
.module
import MT46V32M16
9 from misoclib
.mem
.sdram
.phy
import s6ddrphy
10 from misoclib
.mem
.sdram
.core
.lasmicon
import LASMIconSettings
11 from misoclib
.mem
.flash
import norflash16
12 from misoclib
.video
import framebuffer
13 from misoclib
.soc
import mem_decoder
14 from misoclib
.soc
.sdram
import SDRAMSoC
15 from misoclib
.com
import gpio
16 from misoclib
.com
.liteethmini
.phy
import LiteEthPHY
17 from misoclib
.com
.liteethmini
.mac
import LiteEthMAC
21 def __init__(self
, pads
, outfreq1x
):
22 self
.clock_domains
.cd_sys
= ClockDomain()
23 self
.clock_domains
.cd_sdram_half
= ClockDomain()
24 self
.clock_domains
.cd_sdram_full_wr
= ClockDomain()
25 self
.clock_domains
.cd_sdram_full_rd
= ClockDomain()
26 self
.clock_domains
.cd_base50
= ClockDomain(reset_less
=True)
28 self
.clk4x_wr_strb
= Signal()
29 self
.clk4x_rd_strb
= Signal()
34 ratio
= Fraction(outfreq1x
)/Fraction(infreq
)
35 in_period
= float(Fraction(1000000000)/Fraction(infreq
))
37 self
.specials
+= Instance("mxcrg",
38 Instance
.Parameter("in_period", in_period
),
39 Instance
.Parameter("f_mult", ratio
.numerator
),
40 Instance
.Parameter("f_div", ratio
.denominator
),
41 Instance
.Input("clk50_pad", pads
.clk50
),
42 Instance
.Input("trigger_reset", pads
.trigger_reset
),
44 Instance
.Output("sys_clk", self
.cd_sys
.clk
),
45 Instance
.Output("sys_rst", self
.cd_sys
.rst
),
46 Instance
.Output("clk2x_270", self
.cd_sdram_half
.clk
),
47 Instance
.Output("clk4x_wr", self
.cd_sdram_full_wr
.clk
),
48 Instance
.Output("clk4x_rd", self
.cd_sdram_full_rd
.clk
),
49 Instance
.Output("base50_clk", self
.cd_base50
.clk
),
51 Instance
.Output("clk4x_wr_strb", self
.clk4x_wr_strb
),
52 Instance
.Output("clk4x_rd_strb", self
.clk4x_rd_strb
),
53 Instance
.Output("norflash_rst_n", pads
.norflash_rst_n
),
54 Instance
.Output("ddr_clk_pad_p", pads
.ddr_clk_p
),
55 Instance
.Output("ddr_clk_pad_n", pads
.ddr_clk_n
))
59 def __init__(self
, platform
):
60 self
.clk50
= platform
.request("clk50")
61 self
.trigger_reset
= 0
63 self
.trigger_reset
= platform
.request("user_btn", 1)
64 except ConstraintError
:
66 self
.norflash_rst_n
= platform
.request("norflash_rst_n")
67 ddram_clock
= platform
.request("ddram_clock")
68 self
.ddr_clk_p
= ddram_clock
.p
69 self
.ddr_clk_n
= ddram_clock
.n
72 class BaseSoC(SDRAMSoC
):
73 default_platform
= "mixxeo" # also supports m1
75 def __init__(self
, platform
, sdram_controller_settings
=LASMIconSettings(), **kwargs
):
76 SDRAMSoC
.__init
__(self
, platform
,
77 clk_freq
=(83 + Fraction(1, 3))*1000000,
78 cpu_reset_address
=0x00180000,
79 sdram_controller_settings
=sdram_controller_settings
,
82 self
.submodules
.crg
= _MXCRG(_MXClockPads(platform
), self
.clk_freq
)
84 if not self
.integrated_main_ram_size
:
85 self
.submodules
.ddrphy
= s6ddrphy
.S6HalfRateDDRPHY(platform
.request("ddram"),
86 MT46V32M16(self
.clk_freq
),
89 dqs_ddr_alignment
="C1")
90 self
.register_sdram_phy(self
.ddrphy
)
92 self
.ddrphy
.clk4x_wr_strb
.eq(self
.crg
.clk4x_wr_strb
),
93 self
.ddrphy
.clk4x_rd_strb
.eq(self
.crg
.clk4x_rd_strb
)
96 if not self
.integrated_rom_size
:
97 clk_period_ns
= 1000000000/self
.clk_freq
98 self
.submodules
.norflash
= norflash16
.NorFlash16(platform
.request("norflash"),
99 ceil(110/clk_period_ns
), ceil(50/clk_period_ns
))
100 self
.flash_boot_address
= 0x001a0000
101 self
.register_rom(self
.norflash
.bus
)
103 platform
.add_platform_command("""
104 INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
105 INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
107 platform
.add_source(os
.path
.join("misoclib", "mxcrg.v"))
110 class MiniSoC(BaseSoC
):
115 csr_map
.update(BaseSoC
.csr_map
)
120 interrupt_map
.update(BaseSoC
.interrupt_map
)
123 "ethmac": 0x30000000, # (shadow @0xb0000000)
125 mem_map
.update(BaseSoC
.mem_map
)
127 def __init__(self
, platform
, **kwargs
):
128 BaseSoC
.__init
__(self
, platform
, **kwargs
)
130 if platform
.name
== "mixxeo":
131 self
.submodules
.leds
= gpio
.GPIOOut(platform
.request("user_led"))
132 if platform
.name
== "m1":
133 self
.submodules
.buttons
= gpio
.GPIOIn(Cat(platform
.request("user_btn", 0),
134 platform
.request("user_btn", 2)))
135 self
.submodules
.leds
= gpio
.GPIOOut(Cat(platform
.request("user_led", i
) for i
in range(2)))
137 self
.submodules
.ethphy
= LiteEthPHY(platform
.request("eth_clocks"),
138 platform
.request("eth"))
139 self
.submodules
.ethmac
= LiteEthMAC(phy
=self
.ethphy
, dw
=32, interface
="wishbone")
140 self
.add_wb_slave(mem_decoder(self
.mem_map
["ethmac"]), self
.ethmac
.bus
)
141 self
.add_memory_region("ethmac", self
.mem_map
["ethmac"] | self
.shadow_base
, 0x2000)
144 def get_vga_dvi(platform
):
146 pads_vga
= platform
.request("vga_out")
147 except ConstraintError
:
150 pads_dvi
= platform
.request("dvi_out")
151 except ConstraintError
:
154 platform
.add_platform_command("""
155 PIN "dviout_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
157 return pads_vga
, pads_dvi
160 def add_vga_tig(platform
, fb
):
161 platform
.add_platform_command("""
162 NET "{vga_clk}" TNM_NET = "GRPvga_clk";
163 NET "sys_clk" TNM_NET = "GRPsys_clk";
164 TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
165 TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
166 """, vga_clk
=fb
.driver
.clocking
.cd_pix
.clk
)
169 class FramebufferSoC(MiniSoC
):
173 csr_map
.update(MiniSoC
.csr_map
)
175 def __init__(self
, platform
, **kwargs
):
176 MiniSoC
.__init
__(self
, platform
, **kwargs
)
177 pads_vga
, pads_dvi
= get_vga_dvi(platform
)
178 self
.submodules
.fb
= framebuffer
.Framebuffer(pads_vga
, pads_dvi
,
179 self
.sdram
.crossbar
.get_master())
180 add_vga_tig(platform
, self
.fb
)
182 default_subtarget
= FramebufferSoC