targets/mlabs_video.py

   1 import os
   2 from fractions import Fraction
   3
   4 from migen.fhdl.std import *
   5 from mibuild.generic_platform import ConstraintError
   6
   7 from misoclib import lasmicon, mxcrg, norflash16, minimac3, framebuffer, gpio
   8 from misoclib.sdramphy import s6ddrphy
   9 from misoclib.gensoc import SDRAMSoC
  10
  11 class _MXClockPads:
  12         def __init__(self, platform):
  13                 self.clk50 = platform.request("clk50")
  14                 self.trigger_reset = 0
  15                 try:
  16                         self.trigger_reset = platform.request("user_btn", 1)
  17                 except ConstraintError:
  18                         pass
  19                 self.norflash_rst_n = platform.request("norflash_rst_n")
  20                 ddram_clock = platform.request("ddram_clock")
  21                 self.ddr_clk_p = ddram_clock.p
  22                 self.ddr_clk_n = ddram_clock.n
  23                 eth_clocks = platform.request("eth_clocks")
  24                 self.eth_phy_clk = eth_clocks.phy
  25                 self.eth_rx_clk = eth_clocks.rx
  26                 self.eth_tx_clk = eth_clocks.tx
  27
  28 class BaseSoC(SDRAMSoC):
  29         default_platform = "mixxeo" # also supports m1
  30
  31         def __init__(self, platform, **kwargs):
  32                 SDRAMSoC.__init__(self, platform,
  33                         clk_freq=(83 + Fraction(1, 3))*1000000,
  34                         cpu_reset_address=0x00180000,
  35                         **kwargs)
  36
  37                 sdram_geom = lasmicon.GeomSettings(
  38                         bank_a=2,
  39                         row_a=13,
  40                         col_a=10
  41                 )
  42                 sdram_timing = lasmicon.TimingSettings(
  43                         tRP=self.ns(15),
  44                         tRCD=self.ns(15),
  45                         tWR=self.ns(15),
  46                         tWTR=2,
  47                         tREFI=self.ns(7800, False),
  48                         tRFC=self.ns(70),
  49
  50                         req_queue_size=8,
  51                         read_time=32,
  52                         write_time=16
  53                 )
  54                 self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
  55                         rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
  56                 self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing)
  57
  58                 self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
  59                         self.ns(110), self.ns(50))
  60                 self.flash_boot_address = 0x001a0000
  61                 self.register_rom(self.norflash.bus)
  62
  63                 self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
  64                 self.comb += [
  65                         self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
  66                         self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
  67                 ]
  68                 platform.add_platform_command("""
  69 INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
  70 INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
  71
  72 PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
  73 """)
  74                 platform.add_source_dir(os.path.join("verilog", "mxcrg"))
  75
  76 class MiniSoC(BaseSoC):
  77         csr_map = {
  78                 "minimac":              10,
  79         }
  80         csr_map.update(BaseSoC.csr_map)
  81
  82         interrupt_map = {
  83                 "minimac":              2,
  84         }
  85         interrupt_map.update(BaseSoC.interrupt_map)
  86
  87         def __init__(self, platform, **kwargs):
  88                 BaseSoC.__init__(self, platform, **kwargs)
  89
  90                 if platform.name == "mixxeo":
  91                         self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
  92                 if platform.name == "m1":
  93                         self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2)))
  94                         self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", i) for i in range(2)))
  95
  96                 self.submodules.minimac = minimac3.MiniMAC(platform.request("eth"))
  97                 self.add_wb_slave(lambda a: a[26:29] == 3, self.minimac.membus)
  98                 self.add_cpu_memory_region("minimac_mem", 0xb0000000, 0x1800)
  99                 platform.add_source_dir(os.path.join("verilog", "minimac3"))
 100
 101 def get_vga_dvi(platform):
 102         try:
 103                 pads_vga = platform.request("vga_out")
 104         except ConstraintError:
 105                 pads_vga = None
 106         try:
 107                 pads_dvi = platform.request("dvi_out")
 108         except ConstraintError:
 109                 pads_dvi = None
 110         else:
 111                 platform.add_platform_command("""
 112 PIN "dviout_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
 113 """)
 114         return pads_vga, pads_dvi
 115
 116 def add_vga_tig(platform, fb):
 117         platform.add_platform_command("""
 118 NET "{vga_clk}" TNM_NET = "GRPvga_clk";
 119 NET "sys_clk" TNM_NET = "GRPsys_clk";
 120 TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
 121 TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
 122 """, vga_clk=fb.driver.clocking.cd_pix.clk)
 123
 124 class FramebufferSoC(MiniSoC):
 125         csr_map = {
 126                 "fb":                                   11,
 127         }
 128         csr_map.update(MiniSoC.csr_map)
 129
 130         def __init__(self, platform, **kwargs):
 131                 MiniSoC.__init__(self, platform, **kwargs)
 132                 pads_vga, pads_dvi = get_vga_dvi(platform)
 133                 self.submodules.fb = framebuffer.Framebuffer(pads_vga, pads_dvi, self.lasmixbar.get_master())
 134                 add_vga_tig(platform, self.fb)
 135
 136 default_subtarget = FramebufferSoC