1 from migen
.fhdl
.std
import *
2 from migen
.bus
import wishbone
3 from migen
.genlib
.io
import CRG
5 from misoclib
.soc
import SoC
, mem_decoder
6 from misoclib
.com
.liteethmini
.phy
import LiteEthPHY
7 from misoclib
.com
.liteethmini
.mac
import LiteEthMAC
11 def __init__(self
, platform
, **kwargs
):
12 SoC
.__init
__(self
, platform
,
13 clk_freq
=int((1/(platform
.default_clk_period
))*1000000000),
14 integrated_rom_size
=0x8000,
15 integrated_main_ram_size
=16*1024,
17 self
.submodules
.crg
= CRG(platform
.request(platform
.default_clk_name
))
20 class MiniSoC(BaseSoC
):
25 csr_map
.update(BaseSoC
.csr_map
)
30 interrupt_map
.update(BaseSoC
.interrupt_map
)
33 "ethmac": 0x30000000, # (shadow @0xb0000000)
35 mem_map
.update(BaseSoC
.mem_map
)
37 def __init__(self
, platform
, **kwargs
):
38 BaseSoC
.__init
__(self
, platform
, **kwargs
)
40 self
.submodules
.ethphy
= LiteEthPHY(platform
.request("eth_clocks"),
41 platform
.request("eth"))
42 self
.submodules
.ethmac
= LiteEthMAC(phy
=self
.ethphy
, dw
=32,
44 with_preamble_crc
=False)
45 self
.add_wb_slave(mem_decoder(self
.mem_map
["ethmac"]), self
.ethmac
.bus
)
46 self
.add_memory_region("ethmac", self
.mem_map
["ethmac"] | self
.shadow_base
, 0x2000)
48 default_subtarget
= BaseSoC