targets/simple.py

   1 from migen.fhdl.std import *
   2 from migen.bus import wishbone
   3
   4 from misoclib import gpio, spiflash
   5 from misoclib.gensoc import GenSoC
   6
   7 class SimpleSoC(GenSoC):
   8         default_platform = "papilio_pro"
   9
  10         def __init__(self, platform):
  11                 GenSoC.__init__(self, platform,
  12                         clk_freq=32*1000000,
  13                         cpu_reset_address=0x60000)
  14
  15                 # We can't use reset_less as LM32 does require a reset signal
  16                 self.clock_domains.cd_sys = ClockDomain()
  17                 self.comb += self.cd_sys.clk.eq(platform.request("clk32"))
  18                 self.specials += Instance("FD", p_INIT=1, i_D=0, o_Q=self.cd_sys.rst, i_C=ClockSignal())
  19
  20                 # BIOS is in SPI flash
  21                 self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"),
  22                         cmd=0xefef, cmd_width=16, addr_width=24, dummy=4)
  23                 self.flash_boot_address = 0x70000
  24                 self.register_rom(self.spiflash.bus)
  25
  26                 # TODO: use on-board SDRAM instead of block RAM
  27                 sys_ram_size = 32*1024
  28                 self.submodules.sys_ram = wishbone.SRAM(sys_ram_size)
  29                 self.add_wb_slave(lambda a: a[27:29] == 2, self.sys_ram.bus)
  30                 self.add_cpu_memory_region("sdram", 0x40000000, sys_ram_size)
  31
  32                 self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
  33
  34 default_subtarget = SimpleSoC