3 from migen
.bank
import csrgen
4 from migen
.bus
import wishbone
, csr
5 from migen
.bus
import wishbone2csr
6 from migen
.bank
.description
import *
8 from misoclib
import identifier
10 from litescope
.common
import *
11 from litescope
.bridge
.uart2wb
import LiteScopeUART2WB
12 from litescope
.frontend
.io
import LiteScopeIO
13 from litescope
.frontend
.la
import LiteScopeLA
14 from litescope
.core
.port
import LiteScopeTerm
17 def __init__(self
, clk_in
):
18 self
.clock_domains
.cd_sys
= ClockDomain()
19 self
.clock_domains
.cd_por
= ClockDomain(reset_less
=True)
21 # Power on Reset (vendor agnostic)
23 self
.sync
.por
+= rst_n
.eq(1)
25 self
.cd_sys
.clk
.eq(clk_in
),
26 self
.cd_por
.clk
.eq(clk_in
),
27 self
.cd_sys
.rst
.eq(~rst_n
)
39 def __init__(self
, platform
, clk_freq
):
40 self
.clk_freq
= clk_freq
41 # UART <--> Wishbone bridge
42 self
.submodules
.uart2wb
= LiteScopeUART2WB(platform
.request("serial"), clk_freq
, baud
=115200)
44 # CSR bridge 0x00000000 (shadow @0x00000000)
45 self
.submodules
.wishbone2csr
= wishbone2csr
.WB2CSR(bus_csr
=csr
.Interface(self
.csr_data_width
))
46 self
._wb
_masters
= [self
.uart2wb
.wishbone
]
47 self
._wb
_slaves
= [(lambda a
: a
[23:25] == 0, self
.wishbone2csr
.wishbone
)]
48 self
.cpu_csr_regions
= [] # list of (name, origin, busword, csr_list/Memory)
51 self
.submodules
.identifier
= identifier
.Identifier(0, int(clk_freq
), 0)
53 def add_cpu_memory_region(self
, name
, origin
, length
):
54 self
.cpu_memory_regions
.append((name
, origin
, length
))
56 def add_cpu_csr_region(self
, name
, origin
, busword
, obj
):
57 self
.cpu_csr_regions
.append((name
, origin
, busword
, obj
))
59 def do_finalize(self
):
61 self
.submodules
.wishbonecon
= wishbone
.InterconnectShared(self
._wb
_masters
,
62 self
._wb
_slaves
, register
=True)
65 self
.submodules
.csrbankarray
= csrgen
.BankArray(self
,
66 lambda name
, memory
: self
.csr_map
[name
if memory
is None else name
+ "_" + memory
.name_override
],
67 data_width
=self
.csr_data_width
)
68 self
.submodules
.csrcon
= csr
.Interconnect(self
.wishbone2csr
.csr
, self
.csrbankarray
.get_buses())
69 for name
, csrs
, mapaddr
, rmap
in self
.csrbankarray
.banks
:
70 self
.add_cpu_csr_region(name
, 0xe0000000+0x800*mapaddr
, flen(rmap
.bus
.dat_w
), csrs
)
71 for name
, memory
, mapaddr
, mmap
in self
.csrbankarray
.srams
:
72 self
.add_cpu_csr_region(name
, 0xe0000000+0x800*mapaddr
, flen(rmap
.bus
.dat_w
), memory
)
74 class LiteScopeSoC(GenSoC
, AutoCSR
):
75 default_platform
= "de0nano"
80 csr_map
.update(GenSoC
.csr_map
)
81 def __init__(self
, platform
):
83 GenSoC
.__init
__(self
, platform
, clk_freq
)
84 self
.submodules
.crg
= _CRG(platform
.request("clk50"))
86 self
.submodules
.io
= LiteScopeIO(8)
87 self
.leds
= Cat(*[platform
.request("user_led", i
) for i
in range(8)])
88 self
.comb
+= self
.leds
.eq(self
.io
.o
)
100 self
.submodules
.la
= LiteScopeLA(self
.debug
, 512)
101 self
.la
.trigger
.add_port(LiteScopeTerm(self
.la
.dw
))
102 atexit
.register(self
.exit
, platform
)
104 def exit(self
, platform
):
105 if platform
.vns
is not None:
106 self
.la
.export(platform
.vns
, "./test/la.csv")
108 default_subtarget
= LiteScopeSoC