targets/simple.py

   1 from migen.fhdl.std import *
   2
   3 from misoclib.gensoc import GenSoC, IntegratedBIOS
   4
   5 class SimpleSoC(GenSoC, IntegratedBIOS):
   6         def __init__(self, platform):
   7                 GenSoC.__init__(self, platform,
   8                         clk_freq=32*1000000,
   9                         cpu_reset_address=0,
  10                         sram_size=4096)
  11                 IntegratedBIOS.__init__(self)
  12
  13                 # We can't use reset_less as LM32 does require a reset signal
  14                 self.clock_domains.cd_sys = ClockDomain()
  15                 self.comb += self.cd_sys.clk.eq(platform.request("clk32"))
  16                 self.specials += Instance("FD", p_INIT=1, i_D=0, o_Q=self.cd_sys.rst, i_C=ClockSignal())
  17
  18 def get_default_subtarget(platform):
  19         return SimpleSoC