gensoc: support for user-defined UART and add default values for SRAM and L2 sizes
[litex.git] / targets / simple.py
1 from migen.fhdl.std import *
2
3 from misoclib import gpio, spiflash
4 from misoclib.gensoc import GenSoC, IntegratedBIOS
5
6 class SimpleSoC(GenSoC, IntegratedBIOS):
7 def __init__(self, platform):
8 GenSoC.__init__(self, platform,
9 clk_freq=32*1000000,
10 cpu_reset_address=0)
11 IntegratedBIOS.__init__(self)
12
13 # We can't use reset_less as LM32 does require a reset signal
14 self.clock_domains.cd_sys = ClockDomain()
15 self.comb += self.cd_sys.clk.eq(platform.request("clk32"))
16 self.specials += Instance("FD", p_INIT=1, i_D=0, o_Q=self.cd_sys.rst, i_C=ClockSignal())
17
18 self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
19
20 # Map the SPI flash at 0xb0000000 for demo purposes. Later, we'll want to store the BIOS there.
21 self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"),
22 cmd=0xefef, cmd_width=16, addr_width=24, dummy=4)
23 self.add_wb_slave(lambda a: a[26:29] == 3, self.spiflash.bus)
24
25 def get_default_subtarget(platform):
26 return SimpleSoC