targets/simple.py

   1 from migen.fhdl.std import *
   2 from migen.bus import wishbone
   3
   4 from misoclib.gensoc import GenSoC, mem_decoder
   5
   6 class _CRG(Module):
   7         def __init__(self, clk_in):
   8                 self.clock_domains.cd_sys = ClockDomain()
   9                 self.clock_domains.cd_por = ClockDomain(reset_less=True)
  10
  11                 # Power on Reset (vendor agnostic)
  12                 rst_n = Signal()
  13                 self.sync.por += rst_n.eq(1)
  14                 self.comb += [
  15                         self.cd_sys.clk.eq(clk_in),
  16                         self.cd_por.clk.eq(clk_in),
  17                         self.cd_sys.rst.eq(~rst_n)
  18                 ]
  19
  20 class SimpleSoC(GenSoC):
  21         def __init__(self, platform, **kwargs):
  22                 GenSoC.__init__(self, platform,
  23                         clk_freq=int((1/(platform.default_clk_period))*1000000000),
  24                         with_rom=True,
  25                         with_sdram=True, sdram_size=16*1024,
  26                         **kwargs)
  27                 self.submodules.crg = _CRG(platform.request(platform.default_clk_name))
  28
  29 default_subtarget = SimpleSoC