targets/simple.py

   1 from migen.fhdl.std import *
   2 from migen.bus import wishbone
   3
   4 from misoclib.soc import SoC, mem_decoder
   5 from misoclib.com.liteeth.phy import LiteEthPHY
   6 from misoclib.com.liteeth.mac import LiteEthMAC
   7
   8 class BaseSoC(SoC):
   9         def __init__(self, platform, **kwargs):
  10                 SoC.__init__(self, platform,
  11                         clk_freq=int((1/(platform.default_clk_period))*1000000000),
  12                         with_rom=True,
  13                         with_sdram=True, sdram_size=16*1024,
  14                         **kwargs)
  15
  16 class MiniSoC(BaseSoC):
  17         csr_map = {
  18                 "ethphy":               20,
  19                 "ethmac":               21
  20         }
  21         csr_map.update(BaseSoC.csr_map)
  22
  23         interrupt_map = {
  24                 "ethmac":               2,
  25         }
  26         interrupt_map.update(BaseSoC.interrupt_map)
  27
  28         mem_map = {
  29                 "ethmac":       0x30000000, # (shadow @0xb0000000)
  30         }
  31         mem_map.update(BaseSoC.mem_map)
  32
  33         def __init__(self, platform, **kwargs):
  34                 BaseSoC.__init__(self, platform, **kwargs)
  35
  36                 self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"))
  37                 self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", with_hw_preamble_crc=False)
  38                 self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
  39                 self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)
  40
  41 default_subtarget = BaseSoC