targets/simple.py

   1 from migen.fhdl.std import *
   2 from migen.bus import wishbone
   3 from migen.genlib.io import CRG
   4
   5 from misoclib.soc import SoC, mem_decoder
   6 from misoclib.com.liteeth.phy import LiteEthPHY
   7 from misoclib.com.liteeth.mac import LiteEthMAC
   8
   9
  10 class BaseSoC(SoC):
  11     def __init__(self, platform, **kwargs):
  12         SoC.__init__(self, platform,
  13             clk_freq=int((1/(platform.default_clk_period))*1000000000),
  14             integrated_rom_size=0x8000,
  15             integrated_main_ram_size=16*1024,
  16             **kwargs)
  17         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
  18
  19
  20 class MiniSoC(BaseSoC):
  21     csr_map = {
  22         "ethphy": 20,
  23         "ethmac": 21
  24     }
  25     csr_map.update(BaseSoC.csr_map)
  26
  27     interrupt_map = {
  28         "ethmac": 2,
  29     }
  30     interrupt_map.update(BaseSoC.interrupt_map)
  31
  32     mem_map = {
  33         "ethmac": 0x30000000,  # (shadow @0xb0000000)
  34     }
  35     mem_map.update(BaseSoC.mem_map)
  36
  37     def __init__(self, platform, **kwargs):
  38         BaseSoC.__init__(self, platform, **kwargs)
  39
  40         self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"))
  41         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", with_hw_preamble_crc=False)
  42         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
  43         self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)
  44
  45 default_subtarget = BaseSoC