targets/versa.py

   1 from migen.fhdl.std import *
   2 from migen.bus import wishbone
   3 from migen.genlib.io import CRG
   4
   5 from misoclib.soc import SoC
   6
   7
   8 class BaseSoC(SoC):
   9     default_platform = "versa"
  10     def __init__(self, platform, **kwargs):
  11         SoC.__init__(self, platform,
  12                      clk_freq=100*1000000,
  13                      integrated_rom_size=0x8000,
  14                      **kwargs)
  15         self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst_n"))
  16         self.comb += platform.request("user_led", 0).eq(ResetSignal())
  17
  18 default_subtarget = BaseSoC