1 from migen
.fhdl
.std
import *
2 from migen
.bus
import wishbone
3 from migen
.genlib
.io
import CRG
5 from misoclib
.soc
import SoC
9 default_platform
= "versa"
10 def __init__(self
, platform
, **kwargs
):
11 SoC
.__init
__(self
, platform
,
13 integrated_rom_size
=0x8000,
15 self
.submodules
.crg
= CRG(platform
.request("clk100"), ~platform
.request("rst_n"))
16 self
.comb
+= platform
.request("user_led", 0).eq(ResetSignal())
18 default_subtarget
= BaseSoC