5 from nmigen
.back
.verilog
import convert
6 from nmigen
.build
import Platform
8 from c4m
.nmigen
.jtag
import TAP
, IOType
, IOConn
10 class DummyPlatform(Platform
):
13 required_tools
= ["yosys"]
15 def toolchain_prepare(self
, fragment
, name
, **kwargs
):
16 raise NotImplementedError
18 class Top(Elaboratable
):
19 iotypes
= (IOType
.In
, IOType
.Out
, IOType
.TriOut
, IOType
.InTriOut
)
21 def __init__(self
, io_count
):
22 self
.tap
= tap
= TAP()
23 self
.ios
= [tap
.add_io(iotype
=iotype
) for iotype
in self
.iotypes
]
25 self
.sr
= tap
.add_shiftreg(ircode
=3, length
=3)
27 self
.wb
= tap
.add_wishbone(ircodes
=[4, 5, 6], address_width
=16, data_width
=8)
29 def elaborate(self
, platform
):
32 m
.submodules
.tap
= self
.tap
34 m
.d
.comb
+= self
.sr
.i
.eq(self
.sr
.o
)
42 ports
= [top
.tap
.bus
.tck
, top
.tap
.bus
.tms
, top
.tap
.bus
.tdi
, top
.tap
.bus
.tdo
]
44 for sig
in ("i", "o", "oe"):
46 ports
+= [getattr(conn
.core
, sig
), getattr(conn
.pad
, sig
)]
50 top_code
= convert(top
, ports
=ports
, platform
=p
)
51 with
open("code/top.v", "w") as f
:
54 for filename
, code
in p
.extra_files
.items():
55 with
open("code"+ os
.path
.sep
+ filename
, "w") as f
: