plarforms: rename versa/versaecp55g to versa_ecp3/versa_ecp5
[litex.git] / test / test_bitslip.py
1 import unittest
2 import random
3
4 from migen import *
5 from migen.genlib.misc import BitSlip
6
7
8 class BitSlipModel:
9 def __init__(self, data_width, latency):
10 self.data_width = data_width
11 self.latency = latency
12
13 def simulate(self, bitslip, sequence):
14 # prepare sequence for simulation
15 s = [0]*self.latency
16 for d in sequence:
17 s.append(d)
18 # simulate bitslip
19 r = []
20 for i in range(len(s)-1):
21 v = (s[i+1] << self.data_width) | s[i]
22 v = v >> bitslip
23 v &= 2**self.data_width-1
24 r.append(v)
25 return r
26
27
28 def main_generator(dut):
29 dut.o_sequence = []
30 yield dut.value.eq(dut.bitslip)
31 for i, data in enumerate(dut.i_sequence):
32 yield dut.i.eq(data)
33 dut.o_sequence.append((yield dut.o))
34 yield
35
36
37 class TestBitSlip(unittest.TestCase):
38 def bitslip_test(self, data_width, length=128):
39 prng = random.Random(42)
40 sequence = [prng.randrange(2**data_width) for i in range(length)]
41
42 for i in range(data_width):
43 dut = BitSlip(data_width)
44 dut.bitslip = i
45 dut.i_sequence = sequence
46 run_simulation(dut, main_generator(dut))
47
48 model = BitSlipModel(data_width, 4)
49 m_sequence = model.simulate(i, sequence)
50
51 self.assertEqual(dut.o_sequence, m_sequence[:len(dut.o_sequence)])
52
53 def test_bitslip_4b(self):
54 self.bitslip_test(4)
55
56 def test_bitslip_8b(self):
57 self.bitslip_test(8)
58
59 def test_bitslip_16b(self):
60 self.bitslip_test(16)
61
62 def test_bitslip_32b(self):
63 self.bitslip_test(32)
64
65 def test_bitslip_64b(self):
66 self.bitslip_test(64)
67
68 def test_bitslip_128b(self):
69 self.bitslip_test(128)