5 from migen
.genlib
.misc
import BitSlip
9 def __init__(self
, data_width
, latency
):
10 self
.data_width
= data_width
11 self
.latency
= latency
13 def simulate(self
, bitslip
, sequence
):
14 # prepare sequence for simulation
20 for i
in range(len(s
)-1):
21 v
= (s
[i
+1] << self
.data_width
) | s
[i
]
23 v
&= 2**self
.data_width
-1
28 def main_generator(dut
):
30 yield dut
.value
.eq(dut
.bitslip
)
31 for i
, data
in enumerate(dut
.i_sequence
):
33 dut
.o_sequence
.append((yield dut
.o
))
37 class TestBitSlip(unittest
.TestCase
):
38 def bitslip_test(self
, data_width
, length
=128):
39 prng
= random
.Random(42)
40 sequence
= [prng
.randrange(2**data_width
) for i
in range(length
)]
42 for i
in range(data_width
):
43 dut
= BitSlip(data_width
)
45 dut
.i_sequence
= sequence
46 run_simulation(dut
, main_generator(dut
))
48 model
= BitSlipModel(data_width
, 4)
49 m_sequence
= model
.simulate(i
, sequence
)
51 self
.assertEqual(dut
.o_sequence
, m_sequence
[:len(dut
.o_sequence
)])
53 def test_bitslip_4b(self
):
56 def test_bitslip_8b(self
):
59 def test_bitslip_16b(self
):
62 def test_bitslip_32b(self
):
65 def test_bitslip_64b(self
):
68 def test_bitslip_128b(self
):
69 self
.bitslip_test(128)