build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper...
[litex.git] / test / test_gearbox.py
1 import unittest
2 import random
3
4 from migen import *
5 from migen.genlib.cdc import Gearbox
6
7 # TODO:
8 # connect two gearbox together:
9 # first gearbox: iwidth > owidth
10 # second gearbox: iwidth < owidth
11 # use 2 clock domains
12 # compare input data to output data, should be similar
13 # various datawidth/clock ratios
14
15
16 def data_generator(dut):
17 for i in range(256):
18 yield dut.i.eq(i)
19 yield
20 yield
21
22 @passive
23 def data_checker(dut):
24 while True:
25 #print((yield dut.o))
26 yield
27
28
29 class GearboxDUT(Module):
30 def __init__(self):
31 self.submodules.gearbox_down = Gearbox(10, "user", 8, "gearbox")
32 self.submodules.gearbox_up = Gearbox(8, "gearbox", 10, "user")
33 self.comb += self.gearbox_up.i.eq(self.gearbox_down.o)
34 self.i, self.o = self.gearbox_down.i, self.gearbox_up.o
35
36
37 class TestGearbox(unittest.TestCase):
38 def test_gearbox(self):
39 dut = GearboxDUT()
40 generators = {"user": [data_generator(dut), data_checker(dut)]}
41 clocks = {"user": 12.5, "gearbox": 10}
42 run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
43 self.assertEqual(0, 0)