test/test_targets.py

   1 import unittest
   2 import os
   3
   4 from migen import *
   5
   6 from litex.soc.integration.builder import *
   7
   8
   9 def build_test(socs):
  10     errors = 0
  11     for soc in socs:
  12         os.system("rm -rf build")
  13         builder = Builder(soc, output_dir="./build", compile_software=False, compile_gateware=False)
  14         builder.build()
  15         errors += not os.path.isfile("./build/gateware/top.v")
  16     os.system("rm -rf build")
  17     return errors
  18
  19
  20 class TestTargets(unittest.TestCase):
  21     # altera boards
  22     def test_de0nano(self):
  23         from litex.boards.targets.de0nano import BaseSoC
  24         errors = build_test([BaseSoC()])
  25         self.assertEqual(errors, 0)
  26
  27     # xilinx boards
  28     def test_minispartan6(self):
  29         from litex.boards.targets.minispartan6 import BaseSoC
  30         errors = build_test([BaseSoC()])
  31         self.assertEqual(errors, 0)
  32
  33     def test_arty(self):
  34         from litex.boards.targets.arty import BaseSoC, EthernetSoC
  35         errors = build_test([BaseSoC(), EthernetSoC()])
  36         self.assertEqual(errors, 0)
  37
  38     def test_nexys4ddr(self):
  39         from litex.boards.targets.nexys4ddr import BaseSoC
  40         errors = build_test([BaseSoC()])
  41         self.assertEqual(errors, 0)
  42
  43     def test_nexys_video(self):
  44         from litex.boards.targets.nexys_video import BaseSoC, EthernetSoC
  45         errors = build_test([BaseSoC(), EthernetSoC()])
  46         self.assertEqual(errors, 0)
  47
  48     def test_genesys2(self):
  49         from litex.boards.targets.genesys2 import BaseSoC, EthernetSoC
  50         errors = build_test([BaseSoC(), EthernetSoC()])
  51         self.assertEqual(errors, 0)
  52
  53     def test_kc705(self):
  54         from litex.boards.targets.kc705 import BaseSoC, EthernetSoC
  55         errors = build_test([BaseSoC(), EthernetSoC()])
  56         self.assertEqual(errors, 0)
  57
  58     # lattice boards
  59
  60     # build simple design for all platforms
  61     def test_simple(self):
  62         platforms = [
  63             "arty",
  64             "arty_s7",
  65             "de0nano",
  66             "genesys2",
  67             "icestick",
  68             "kc705",
  69             "kcu105",
  70             "machxo3",
  71             "mercury",
  72             "mimasv2",
  73             "minispartan6",
  74             "nexys4ddr",
  75             "nexys_video",
  76             "papilio_pro",
  77             "tinyfpga_b",
  78             "tinyfpga_bx",
  79             "versa",
  80             "versaecp55g"
  81         ]
  82         for p in platforms:
  83             os.system("litex_simple litex.boards.platforms." + p +
  84                 " --no-compile-software " +
  85                 " --no-compile-gateware " +
  86                 " --uart-stub=True")