top.py

   1 from fractions import Fraction
   2 from math import ceil
   3
   4 from migen.fhdl.structure import *
   5 from migen.fhdl import verilog, autofragment
   6 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
   7
   8 from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \
   9         identifier, timer, minimac3, framebuffer, asmiprobe
  10 from cmacros import get_macros
  11 from constraints import Constraints
  12
  13 MHz = 1000000
  14 clk_freq = (83 + Fraction(1, 3))*MHz
  15 sram_size = 4096 # in bytes
  16 l2_size = 8192 # in bytes
  17
  18 clk_period_ns = 1000000000/clk_freq
  19 def ns(t, margin=True):
  20         if margin:
  21                 t += clk_period_ns/2
  22         return ceil(t/clk_period_ns)
  23
  24 sdram_phy = asmicon.PhySettings(
  25         dfi_d=64,
  26         nphases=2,
  27         rdphase=0,
  28         wrphase=1
  29 )
  30 sdram_geom = asmicon.GeomSettings(
  31         bank_a=2,
  32         row_a=13,
  33         col_a=10
  34 )
  35 sdram_timing = asmicon.TimingSettings(
  36         tRP=ns(15),
  37         tRCD=ns(15),
  38         tWR=ns(15),
  39         tREFI=ns(7800, False),
  40         tRFC=ns(70),
  41
  42         CL=3,
  43         rd_delay=4,
  44
  45         read_time=32,
  46         write_time=16
  47 )
  48
  49 csr_macros = get_macros("common/csrbase.h")
  50 def csr_offset(name):
  51         base = int(csr_macros[name + "_BASE"], 0)
  52         assert((base >= 0xe0000000) and (base <= 0xe0010000))
  53         return (base - 0xe0000000)//0x800
  54
  55 interrupt_macros = get_macros("common/interrupt.h")
  56 def interrupt_n(name):
  57         return int(interrupt_macros[name + "_INTERRUPT"], 0)
  58
  59 version = get_macros("common/version.h")["VERSION"][1:-1]
  60
  61 def get():
  62         #
  63         # ASMI
  64         #
  65         asmicon0 = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
  66         asmiport_wb = asmicon0.hub.get_port()
  67         asmiport_fb = asmicon0.hub.get_port(2)
  68         asmicon0.finalize()
  69
  70         #
  71         # DFI
  72         #
  73         ddrphy0 = s6ddrphy.S6DDRPHY(sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d)
  74         dfii0 = dfii.DFIInjector(csr_offset("DFII"),
  75                 sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d, sdram_phy.nphases)
  76         dficon0 = dfi.Interconnect(dfii0.master, ddrphy0.dfi)
  77         dficon1 = dfi.Interconnect(asmicon0.dfi, dfii0.slave)
  78
  79         #
  80         # WISHBONE
  81         #
  82         cpu0 = lm32.LM32()
  83         norflash0 = norflash.NorFlash(25, 12)
  84         sram0 = wishbone.SRAM(sram_size)
  85         minimac0 = minimac3.MiniMAC(csr_offset("MINIMAC"))
  86         wishbone2asmi0 = wishbone2asmi.WB2ASMI(l2_size//4, asmiport_wb)
  87         wishbone2csr0 = wishbone2csr.WB2CSR()
  88
  89         # norflash     0x00000000 (shadow @0x80000000)
  90         # SRAM/debug   0x10000000 (shadow @0x90000000)
  91         # USB          0x20000000 (shadow @0xa0000000)
  92         # Ethernet     0x30000000 (shadow @0xb0000000)
  93         # SDRAM        0x40000000 (shadow @0xc0000000)
  94         # CSR bridge   0x60000000 (shadow @0xe0000000)
  95         wishbonecon0 = wishbone.InterconnectShared(
  96                 [
  97                         cpu0.ibus,
  98                         cpu0.dbus
  99                 ], [
 100                         (lambda a: a[26:29] == 0, norflash0.bus),
 101                         (lambda a: a[26:29] == 1, sram0.bus),
 102                         (lambda a: a[26:29] == 3, minimac0.membus),
 103                         (lambda a: a[27:29] == 2, wishbone2asmi0.wishbone),
 104                         (lambda a: a[27:29] == 3, wishbone2csr0.wishbone)
 105                 ],
 106                 register=True)
 107
 108         #
 109         # CSR
 110         #
 111         uart0 = uart.UART(csr_offset("UART"), clk_freq, baud=115200)
 112         identifier0 = identifier.Identifier(csr_offset("ID"), 0x4D31, version, int(clk_freq))
 113         timer0 = timer.Timer(csr_offset("TIMER0"))
 114         fb0 = framebuffer.Framebuffer(csr_offset("FB"), asmiport_fb)
 115         asmiprobe0 = asmiprobe.ASMIprobe(csr_offset("ASMIPROBE"), asmicon0.hub)
 116         csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
 117                 uart0.bank.bus,
 118                 dfii0.bank.bus,
 119                 identifier0.bank.bus,
 120                 timer0.bank.bus,
 121                 minimac0.bank.bus,
 122                 fb0.bank.bus,
 123                 asmiprobe0.bank.bus
 124         ])
 125
 126         #
 127         # Interrupts
 128         #
 129         interrupts = Fragment([
 130                 cpu0.interrupt[interrupt_n("UART")].eq(uart0.events.irq),
 131                 cpu0.interrupt[interrupt_n("TIMER0")].eq(timer0.events.irq),
 132                 cpu0.interrupt[interrupt_n("MINIMAC")].eq(minimac0.events.irq)
 133         ])
 134
 135         #
 136         # Housekeeping
 137         #
 138         crg0 = m1crg.M1CRG(50*MHz, clk_freq)
 139
 140         ddrphy_strobes = Fragment([
 141                 ddrphy0.clk4x_wr_strb.eq(crg0.clk4x_wr_strb),
 142                 ddrphy0.clk4x_rd_strb.eq(crg0.clk4x_rd_strb)
 143         ])
 144         frag = autofragment.from_local() \
 145                 + interrupts \
 146                 + ddrphy_strobes
 147         cst = Constraints(crg0, norflash0, uart0, ddrphy0, minimac0, fb0)
 148         src_verilog, vns = verilog.convert(frag,
 149                 cst.get_ios(),
 150                 name="soc",
 151                 clock_domains={
 152                         "sys": crg0.cd_sys,
 153                         "sys2x_270": crg0.cd_sys2x_270,
 154                         "sys4x_wr": crg0.cd_sys4x_wr,
 155                         "sys4x_rd": crg0.cd_sys4x_rd,
 156                         "vga": crg0.cd_vga
 157                 },
 158                 return_ns=True)
 159         src_ucf = cst.get_ucf(vns)
 160         return (src_verilog, src_ucf)