top.py

   1 from fractions import Fraction
   2 from math import ceil
   3
   4 from migen.fhdl.structure import *
   5 from migen.fhdl.module import Module
   6 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
   7 from migen.bank import csrgen
   8
   9 from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \
  10         identifier, timer, minimac3, framebuffer, asmiprobe, dvisampler
  11 from cmacros import get_macros
  12
  13 MHz = 1000000
  14 clk_freq = (83 + Fraction(1, 3))*MHz
  15 sram_size = 4096 # in bytes
  16 l2_size = 8192 # in bytes
  17
  18 clk_period_ns = 1000000000/clk_freq
  19 def ns(t, margin=True):
  20         if margin:
  21                 t += clk_period_ns/2
  22         return ceil(t/clk_period_ns)
  23
  24 sdram_phy = asmicon.PhySettings(
  25         dfi_d=64,
  26         nphases=2,
  27         rdphase=0,
  28         wrphase=1
  29 )
  30 sdram_geom = asmicon.GeomSettings(
  31         bank_a=2,
  32         row_a=13,
  33         col_a=10
  34 )
  35 sdram_timing = asmicon.TimingSettings(
  36         tRP=ns(15),
  37         tRCD=ns(15),
  38         tWR=ns(15),
  39         tREFI=ns(7800, False),
  40         tRFC=ns(70),
  41
  42         CL=3,
  43         rd_delay=4,
  44
  45         read_time=32,
  46         write_time=16
  47 )
  48
  49 csr_macros = get_macros("common/csrbase.h")
  50 def csr_offset(name):
  51         base = int(csr_macros[name + "_BASE"], 0)
  52         assert((base >= 0xe0000000) and (base <= 0xe0010000))
  53         return (base - 0xe0000000)//0x800
  54
  55 interrupt_macros = get_macros("common/interrupt.h")
  56 def interrupt_n(name):
  57         return int(interrupt_macros[name + "_INTERRUPT"], 0)
  58
  59 version = get_macros("common/version.h")["VERSION"][1:-1]
  60
  61 def csr_address_map(name, memory):
  62         if memory is not None:
  63                 name += "_" + memory.name_override
  64         return csr_offset(name.upper())
  65
  66 class SoC(Module):
  67         def __init__(self):
  68                 #
  69                 # ASMI
  70                 #
  71                 self.submodules.asmicon = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
  72                 asmiport_wb = self.asmicon.hub.get_port()
  73                 asmiport_fb = self.asmicon.hub.get_port(2)
  74                 self.asmicon.finalize()
  75
  76                 #
  77                 # DFI
  78                 #
  79                 self.submodules.ddrphy = s6ddrphy.S6DDRPHY(sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d)
  80                 self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d,
  81                         sdram_phy.nphases)
  82                 self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, self.ddrphy.dfi)
  83                 self.submodules.dficon1 = dfi.Interconnect(self.asmicon.dfi, self.dfii.slave)
  84
  85                 #
  86                 # WISHBONE
  87                 #
  88                 self.submodules.cpu = lm32.LM32()
  89                 self.submodules.norflash = norflash.NorFlash(25, 12)
  90                 self.submodules.sram = wishbone.SRAM(sram_size)
  91                 self.submodules.minimac = minimac3.MiniMAC()
  92                 self.submodules.wishbone2asmi = wishbone2asmi.WB2ASMI(l2_size//4, asmiport_wb)
  93                 self.submodules.wishbone2csr = wishbone2csr.WB2CSR()
  94
  95                 # norflash     0x00000000 (shadow @0x80000000)
  96                 # SRAM/debug   0x10000000 (shadow @0x90000000)
  97                 # USB          0x20000000 (shadow @0xa0000000)
  98                 # Ethernet     0x30000000 (shadow @0xb0000000)
  99                 # SDRAM        0x40000000 (shadow @0xc0000000)
 100                 # CSR bridge   0x60000000 (shadow @0xe0000000)
 101                 self.submodules.wishbonecon = wishbone.InterconnectShared(
 102                         [
 103                                 self.cpu.ibus,
 104                                 self.cpu.dbus
 105                         ], [
 106                                 (lambda a: a[26:29] == 0, self.norflash.bus),
 107                                 (lambda a: a[26:29] == 1, self.sram.bus),
 108                                 (lambda a: a[26:29] == 3, self.minimac.membus),
 109                                 (lambda a: a[27:29] == 2, self.wishbone2asmi.wishbone),
 110                                 (lambda a: a[27:29] == 3, self.wishbone2csr.wishbone)
 111                         ],
 112                         register=True)
 113
 114                 #
 115                 # CSR
 116                 #
 117                 self.submodules.uart = uart.UART(clk_freq, baud=115200)
 118                 self.submodules.identifier = identifier.Identifier(0x4D31, version, int(clk_freq))
 119                 self.submodules.timer0 = timer.Timer()
 120                 self.submodules.fb = framebuffer.Framebuffer(asmiport_fb)
 121                 self.submodules.asmiprobe = asmiprobe.ASMIprobe(self.asmicon.hub)
 122                 self.submodules.dvisampler0 = dvisampler.DVISampler("02")
 123                 self.submodules.dvisampler1 = dvisampler.DVISampler("02")
 124
 125                 self.submodules.csrbankarray = csrgen.BankArray(self, csr_address_map)
 126                 self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
 127
 128                 #
 129                 # Interrupts
 130                 #
 131                 self.comb += [
 132                         self.cpu.interrupt[interrupt_n("UART")].eq(self.uart.ev.irq),
 133                         self.cpu.interrupt[interrupt_n("TIMER0")].eq(self.timer0.ev.irq),
 134                         self.cpu.interrupt[interrupt_n("MINIMAC")].eq(self.minimac.ev.irq)
 135                 ]
 136
 137                 #
 138                 # Clocking
 139                 #
 140                 self.submodules.crg = m1crg.M1CRG(50*MHz, clk_freq)
 141                 self.comb += [
 142                         self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
 143                         self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
 144                 ]