top.py

   1 from fractions import Fraction
   2 from math import ceil
   3
   4 from migen.fhdl.structure import *
   5 from migen.fhdl import verilog, autofragment
   6 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
   7
   8 from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, \
   9         identifier, timer, minimac3, framebuffer, asmiprobe
  10 from cmacros import get_macros
  11 from constraints import Constraints
  12
  13 MHz = 1000000
  14 clk_freq = (83 + Fraction(1, 3))*MHz
  15 sram_size = 4096 # in bytes
  16 l2_size = 8192 # in bytes
  17
  18 clk_period_ns = 1000000000/clk_freq
  19 def ns(t, margin=True):
  20         if margin:
  21                 t += clk_period_ns/2
  22         return ceil(t/clk_period_ns)
  23
  24 sdram_phy = asmicon.PhySettings(
  25         dfi_d=64,
  26         nphases=2,
  27         rdphase=0,
  28         wrphase=1
  29 )
  30 sdram_geom = asmicon.GeomSettings(
  31         bank_a=2,
  32         row_a=13,
  33         col_a=10
  34 )
  35 sdram_timing = asmicon.TimingSettings(
  36         tRP=ns(15),
  37         tRCD=ns(15),
  38         tWR=ns(15),
  39         tREFI=ns(7800, False),
  40         tRFC=ns(70),
  41
  42         CL=3,
  43         rd_delay=4,
  44
  45         read_time=32,
  46         write_time=16
  47 )
  48
  49 def ddrphy_clocking(crg, phy):
  50         names = [
  51                 "clk2x_270",
  52                 "clk4x_wr",
  53                 "clk4x_wr_strb",
  54                 "clk4x_rd",
  55                 "clk4x_rd_strb"
  56         ]
  57         comb = [getattr(phy, name).eq(getattr(crg, name)) for name in names]
  58         return Fragment(comb)
  59
  60 csr_macros = get_macros("common/csrbase.h")
  61 def csr_offset(name):
  62         base = int(csr_macros[name + "_BASE"], 0)
  63         assert((base >= 0xe0000000) and (base <= 0xe0010000))
  64         return (base - 0xe0000000)//0x800
  65
  66 interrupt_macros = get_macros("common/interrupt.h")
  67 def interrupt_n(name):
  68         return int(interrupt_macros[name + "_INTERRUPT"], 0)
  69
  70 version = get_macros("common/version.h")["VERSION"][1:-1]
  71
  72 def get():
  73         #
  74         # ASMI
  75         #
  76         asmicon0 = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
  77         asmiport_wb = asmicon0.hub.get_port()
  78         asmiport_fb = asmicon0.hub.get_port(2)
  79         asmicon0.finalize()
  80
  81         #
  82         # DFI
  83         #
  84         ddrphy0 = s6ddrphy.S6DDRPHY(sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d)
  85         dfii0 = dfii.DFIInjector(csr_offset("DFII"),
  86                 sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d, sdram_phy.nphases)
  87         dficon0 = dfi.Interconnect(dfii0.master, ddrphy0.dfi)
  88         dficon1 = dfi.Interconnect(asmicon0.dfi, dfii0.slave)
  89
  90         #
  91         # WISHBONE
  92         #
  93         cpu0 = lm32.LM32()
  94         norflash0 = norflash.NorFlash(25, 12)
  95         sram0 = sram.SRAM(sram_size//4)
  96         minimac0 = minimac3.MiniMAC(csr_offset("MINIMAC"))
  97         wishbone2asmi0 = wishbone2asmi.WB2ASMI(l2_size//4, asmiport_wb)
  98         wishbone2csr0 = wishbone2csr.WB2CSR()
  99
 100         # norflash     0x00000000 (shadow @0x80000000)
 101         # SRAM/debug   0x10000000 (shadow @0x90000000)
 102         # USB          0x20000000 (shadow @0xa0000000)
 103         # Ethernet     0x30000000 (shadow @0xb0000000)
 104         # SDRAM        0x40000000 (shadow @0xc0000000)
 105         # CSR bridge   0x60000000 (shadow @0xe0000000)
 106         wishbonecon0 = wishbone.InterconnectShared(
 107                 [
 108                         cpu0.ibus,
 109                         cpu0.dbus
 110                 ], [
 111                         (binc("000"), norflash0.bus),
 112                         (binc("001"), sram0.bus),
 113                         (binc("011"), minimac0.membus),
 114                         (binc("10"), wishbone2asmi0.wishbone),
 115                         (binc("11"), wishbone2csr0.wishbone)
 116                 ],
 117                 register=True,
 118                 offset=1)
 119
 120         #
 121         # CSR
 122         #
 123         uart0 = uart.UART(csr_offset("UART"), clk_freq, baud=115200)
 124         identifier0 = identifier.Identifier(csr_offset("ID"), 0x4D31, version, int(clk_freq))
 125         timer0 = timer.Timer(csr_offset("TIMER0"))
 126         fb0 = framebuffer.Framebuffer(csr_offset("FB"), asmiport_fb)
 127         asmiprobe0 = asmiprobe.ASMIprobe(csr_offset("ASMIPROBE"), asmicon0.hub)
 128         csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
 129                 uart0.bank.interface,
 130                 dfii0.bank.interface,
 131                 identifier0.bank.interface,
 132                 timer0.bank.interface,
 133                 minimac0.bank.interface,
 134                 fb0.bank.interface,
 135                 asmiprobe0.bank.interface
 136         ])
 137
 138         #
 139         # Interrupts
 140         #
 141         interrupts = Fragment([
 142                 cpu0.interrupt[interrupt_n("UART")].eq(uart0.events.irq),
 143                 cpu0.interrupt[interrupt_n("TIMER0")].eq(timer0.events.irq),
 144                 cpu0.interrupt[interrupt_n("MINIMAC")].eq(minimac0.events.irq)
 145         ])
 146
 147         #
 148         # Housekeeping
 149         #
 150         crg0 = m1crg.M1CRG(50*MHz, clk_freq)
 151
 152         vga_clocking = Fragment([
 153                 fb0.vga_clk.eq(crg0.vga_clk)
 154         ])
 155         frag = autofragment.from_local() \
 156                 + interrupts \
 157                 + ddrphy_clocking(crg0, ddrphy0) \
 158                 + vga_clocking
 159         cst = Constraints(crg0, norflash0, uart0, ddrphy0, minimac0, fb0)
 160         src_verilog, vns = verilog.convert(frag,
 161                 cst.get_ios(),
 162                 name="soc",
 163                 clk_signal=crg0.sys_clk,
 164                 rst_signal=crg0.sys_rst,
 165                 return_ns=True)
 166         src_ucf = cst.get_ucf(vns)
 167         return (src_verilog, src_ucf)