top.py

   1 from migen.fhdl.structure import *
   2 from migen.fhdl import tools, verilog, autofragment
   3 from migen.bus import wishbone, csr, wishbone2csr
   4
   5 from milkymist import m1reset, clkfx, lm32, norflash, uart, sram
   6 import constraints
   7
   8 def get():
   9         MHz = 1000000
  10         clk_freq = 80*MHz
  11         sram_size = 4096 # in kilobytes
  12
  13         clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
  14         reset0 = m1reset.M1Reset()
  15
  16         cpu0 = lm32.LM32()
  17         norflash0 = norflash.NorFlash(25, 12)
  18         sram0 = sram.SRAM(sram_size//4)
  19         wishbone2csr0 = wishbone2csr.WB2CSR()
  20         wishbonecon0 = wishbone.InterconnectShared(
  21                 [cpu0.ibus, cpu0.dbus],
  22                 [(0, norflash0.bus), (1, sram0.bus), (3, wishbone2csr0.wishbone)],
  23                 register=True,
  24                 offset=1)
  25         uart0 = uart.UART(0, clk_freq, baud=115200)
  26         csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
  27
  28         frag = autofragment.from_local()
  29         src_verilog, vns = verilog.convert(frag,
  30                 {clkfx_sys.clkin, reset0.trigger_reset},
  31                 name="soc",
  32                 clk_signal=clkfx_sys.clkout,
  33                 rst_signal=reset0.sys_rst,
  34                 return_ns=True)
  35         src_ucf = constraints.get(vns, clkfx_sys, reset0, norflash0, uart0)
  36         return (src_verilog, src_ucf)