top.py

   1 from fractions import Fraction
   2 from math import ceil
   3
   4 from migen.fhdl.structure import *
   5 from migen.fhdl import verilog, autofragment
   6 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
   7
   8 from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, identifier, minimac3
   9 from cmacros import get_macros
  10 from constraints import Constraints
  11
  12 MHz = 1000000
  13 clk_freq = (83 + Fraction(1, 3))*MHz
  14 sram_size = 4096 # in bytes
  15 l2_size = 8192 # in bytes
  16
  17 clk_period_ns = 1000000000/clk_freq
  18 def ns(t, margin=True):
  19         if margin:
  20                 t += clk_period_ns/2
  21         return ceil(t/clk_period_ns)
  22
  23 sdram_phy = asmicon.PhySettings(
  24         dfi_d=64,
  25         nphases=2,
  26         rdphase=0,
  27         wrphase=1
  28 )
  29 sdram_geom = asmicon.GeomSettings(
  30         bank_a=2,
  31         row_a=13,
  32         col_a=10
  33 )
  34 sdram_timing = asmicon.TimingSettings(
  35         tRP=ns(15),
  36         tRCD=ns(15),
  37         tWR=ns(15),
  38         tREFI=ns(7800, False),
  39         tRFC=ns(70),
  40
  41         CL=3,
  42         rd_delay=4,
  43
  44         slot_time=16,
  45         read_time=32,
  46         write_time=16
  47 )
  48
  49 def ddrphy_clocking(crg, phy):
  50         names = [
  51                 "clk2x_270",
  52                 "clk4x_wr",
  53                 "clk4x_wr_strb",
  54                 "clk4x_rd",
  55                 "clk4x_rd_strb"
  56         ]
  57         comb = [getattr(phy, name).eq(getattr(crg, name)) for name in names]
  58         return Fragment(comb)
  59
  60 csr_macros = get_macros("common/csrbase.h")
  61 def csr_offset(name):
  62         base = int(csr_macros[name + "_BASE"], 0)
  63         assert((base >= 0xe0000000) and (base <= 0xe0010000))
  64         return (base - 0xe0000000)//0x800
  65
  66 version = get_macros("common/version.h")["VERSION"][1:-1]
  67
  68 def get():
  69         #
  70         # ASMI
  71         #
  72         asmicon0 = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
  73         asmiport_wb = asmicon0.hub.get_port()
  74         asmicon0.finalize()
  75
  76         #
  77         # DFI
  78         #
  79         ddrphy0 = s6ddrphy.S6DDRPHY(sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d)
  80         dfii0 = dfii.DFIInjector(csr_offset("DFII"),
  81                 sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d, sdram_phy.nphases)
  82         dficon0 = dfi.Interconnect(dfii0.master, ddrphy0.dfi)
  83         dficon1 = dfi.Interconnect(asmicon0.dfi, dfii0.slave)
  84
  85         #
  86         # WISHBONE
  87         #
  88         cpu0 = lm32.LM32()
  89         norflash0 = norflash.NorFlash(25, 12)
  90         sram0 = sram.SRAM(sram_size//4)
  91         minimac0 = minimac3.MiniMAC(csr_offset("MINIMAC"))
  92         wishbone2asmi0 = wishbone2asmi.WB2ASMI(l2_size//4, asmiport_wb)
  93         wishbone2csr0 = wishbone2csr.WB2CSR()
  94
  95         # norflash     0x00000000 (shadow @0x80000000)
  96         # SRAM/debug   0x10000000 (shadow @0x90000000)
  97         # USB          0x20000000 (shadow @0xa0000000)
  98         # Ethernet     0x30000000 (shadow @0xb0000000)
  99         # SDRAM        0x40000000 (shadow @0xc0000000)
 100         # CSR bridge   0x60000000 (shadow @0xe0000000)
 101         wishbonecon0 = wishbone.InterconnectShared(
 102                 [
 103                         cpu0.ibus,
 104                         cpu0.dbus
 105                 ], [
 106                         (binc("000"), norflash0.bus),
 107                         (binc("001"), sram0.bus),
 108                         (binc("011"), minimac0.membus),
 109                         (binc("10"), wishbone2asmi0.wishbone),
 110                         (binc("11"), wishbone2csr0.wishbone)
 111                 ],
 112                 register=True,
 113                 offset=1)
 114
 115         #
 116         # CSR
 117         #
 118         uart0 = uart.UART(csr_offset("UART"), clk_freq, baud=115200)
 119         identifier0 = identifier.Identifier(csr_offset("ID"), 0x4D31, version)
 120         csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
 121                 uart0.bank.interface,
 122                 dfii0.bank.interface,
 123                 identifier0.bank.interface,
 124                 minimac0.bank.interface
 125         ])
 126
 127         #
 128         # Interrupts
 129         #
 130         interrupts = Fragment([
 131                 cpu0.interrupt[0].eq(uart0.events.irq)
 132         ])
 133
 134         #
 135         # Housekeeping
 136         #
 137         crg0 = m1crg.M1CRG(50*MHz, clk_freq)
 138
 139         frag = autofragment.from_local() + interrupts + ddrphy_clocking(crg0, ddrphy0)
 140         cst = Constraints(crg0, norflash0, uart0, ddrphy0, minimac0)
 141         src_verilog, vns = verilog.convert(frag,
 142                 cst.get_ios(),
 143                 name="soc",
 144                 clk_signal=crg0.sys_clk,
 145                 rst_signal=crg0.sys_rst,
 146                 return_ns=True)
 147         src_ucf = cst.get_ucf(vns)
 148         return (src_verilog, src_ucf)