top.py

   1 from fractions import Fraction
   2 from math import ceil
   3
   4 from migen.fhdl.structure import *
   5 from migen.fhdl import verilog, autofragment
   6 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
   7
   8 from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \
   9         identifier, timer, minimac3, framebuffer, asmiprobe
  10 from cmacros import get_macros
  11
  12 MHz = 1000000
  13 clk_freq = (83 + Fraction(1, 3))*MHz
  14 sram_size = 4096 # in bytes
  15 l2_size = 8192 # in bytes
  16
  17 clk_period_ns = 1000000000/clk_freq
  18 def ns(t, margin=True):
  19         if margin:
  20                 t += clk_period_ns/2
  21         return ceil(t/clk_period_ns)
  22
  23 sdram_phy = asmicon.PhySettings(
  24         dfi_d=64,
  25         nphases=2,
  26         rdphase=0,
  27         wrphase=1
  28 )
  29 sdram_geom = asmicon.GeomSettings(
  30         bank_a=2,
  31         row_a=13,
  32         col_a=10
  33 )
  34 sdram_timing = asmicon.TimingSettings(
  35         tRP=ns(15),
  36         tRCD=ns(15),
  37         tWR=ns(15),
  38         tREFI=ns(7800, False),
  39         tRFC=ns(70),
  40
  41         CL=3,
  42         rd_delay=4,
  43
  44         read_time=32,
  45         write_time=16
  46 )
  47
  48 csr_macros = get_macros("common/csrbase.h")
  49 def csr_offset(name):
  50         base = int(csr_macros[name + "_BASE"], 0)
  51         assert((base >= 0xe0000000) and (base <= 0xe0010000))
  52         return (base - 0xe0000000)//0x800
  53
  54 interrupt_macros = get_macros("common/interrupt.h")
  55 def interrupt_n(name):
  56         return int(interrupt_macros[name + "_INTERRUPT"], 0)
  57
  58 version = get_macros("common/version.h")["VERSION"][1:-1]
  59
  60 class SoC:
  61         def __init__(self):
  62                 #
  63                 # ASMI
  64                 #
  65                 self.asmicon = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
  66                 asmiport_wb = self.asmicon.hub.get_port()
  67                 asmiport_fb = self.asmicon.hub.get_port(2)
  68                 self.asmicon.finalize()
  69
  70                 #
  71                 # DFI
  72                 #
  73                 self.ddrphy = s6ddrphy.S6DDRPHY(sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d)
  74                 self.dfii = dfii.DFIInjector(csr_offset("DFII"),
  75                         sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d, sdram_phy.nphases)
  76                 self.dficon0 = dfi.Interconnect(self.dfii.master, self.ddrphy.dfi)
  77                 self.dficon1 = dfi.Interconnect(self.asmicon.dfi, self.dfii.slave)
  78
  79                 #
  80                 # WISHBONE
  81                 #
  82                 self.cpu = lm32.LM32()
  83                 self.norflash = norflash.NorFlash(25, 12)
  84                 self.sram = wishbone.SRAM(sram_size)
  85                 self.minimac = minimac3.MiniMAC(csr_offset("MINIMAC"))
  86                 self.wishbone2asmi = wishbone2asmi.WB2ASMI(l2_size//4, asmiport_wb)
  87                 self.wishbone2csr = wishbone2csr.WB2CSR()
  88
  89                 # norflash     0x00000000 (shadow @0x80000000)
  90                 # SRAM/debug   0x10000000 (shadow @0x90000000)
  91                 # USB          0x20000000 (shadow @0xa0000000)
  92                 # Ethernet     0x30000000 (shadow @0xb0000000)
  93                 # SDRAM        0x40000000 (shadow @0xc0000000)
  94                 # CSR bridge   0x60000000 (shadow @0xe0000000)
  95                 self.wishbonecon = wishbone.InterconnectShared(
  96                         [
  97                                 self.cpu.ibus,
  98                                 self.cpu.dbus
  99                         ], [
 100                                 (lambda a: a[26:29] == 0, self.norflash.bus),
 101                                 (lambda a: a[26:29] == 1, self.sram.bus),
 102                                 (lambda a: a[26:29] == 3, self.minimac.membus),
 103                                 (lambda a: a[27:29] == 2, self.wishbone2asmi.wishbone),
 104                                 (lambda a: a[27:29] == 3, self.wishbone2csr.wishbone)
 105                         ],
 106                         register=True)
 107
 108                 #
 109                 # CSR
 110                 #
 111                 self.uart = uart.UART(csr_offset("UART"), clk_freq, baud=115200)
 112                 self.identifier = identifier.Identifier(csr_offset("ID"), 0x4D31, version, int(clk_freq))
 113                 self.timer = timer.Timer(csr_offset("TIMER0"))
 114                 self.fb = framebuffer.Framebuffer(csr_offset("FB"), asmiport_fb)
 115                 self.asmiprobe = asmiprobe.ASMIprobe(csr_offset("ASMIPROBE"), self.asmicon.hub)
 116                 self.csrcon = csr.Interconnect(self.wishbone2csr.csr, [
 117                         self.uart.bank.bus,
 118                         self.dfii.bank.bus,
 119                         self.identifier.bank.bus,
 120                         self.timer.bank.bus,
 121                         self.minimac.bank.bus,
 122                         self.fb.bank.bus,
 123                         self.asmiprobe.bank.bus
 124                 ])
 125
 126                 #
 127                 # Clocking
 128                 #
 129                 self.crg = m1crg.M1CRG(50*MHz, clk_freq)
 130
 131         def get_fragment(self):
 132                 comb = [
 133                         #
 134                         # Interrupts
 135                         #
 136                         self.cpu.interrupt[interrupt_n("UART")].eq(self.uart.events.irq),
 137                         self.cpu.interrupt[interrupt_n("TIMER0")].eq(self.timer.events.irq),
 138                         self.cpu.interrupt[interrupt_n("MINIMAC")].eq(self.minimac.events.irq),
 139                         #
 140                         # DDR PHY strobes
 141                         #
 142                         self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
 143                         self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
 144                 ]
 145                 glue = Fragment(comb)
 146                 return glue + autofragment.from_attributes(self)