1 from fractions
import Fraction
4 from migen
.fhdl
.structure
import *
5 from migen
.fhdl
import verilog
, autofragment
6 from migen
.bus
import wishbone
, wishbone2asmi
, csr
, wishbone2csr
, dfi
8 from milkymist
import m1crg
, lm32
, norflash
, uart
, s6ddrphy
, dfii
, asmicon
, \
9 identifier
, timer
, minimac3
, framebuffer
, asmiprobe
10 from cmacros
import get_macros
13 clk_freq
= (83 + Fraction(1, 3))*MHz
14 sram_size
= 4096 # in bytes
15 l2_size
= 8192 # in bytes
17 clk_period_ns
= 1000000000/clk_freq
18 def ns(t
, margin
=True):
21 return ceil(t
/clk_period_ns
)
23 sdram_phy
= asmicon
.PhySettings(
29 sdram_geom
= asmicon
.GeomSettings(
34 sdram_timing
= asmicon
.TimingSettings(
38 tREFI
=ns(7800, False),
48 csr_macros
= get_macros("common/csrbase.h")
50 base
= int(csr_macros
[name
+ "_BASE"], 0)
51 assert((base
>= 0xe0000000) and (base
<= 0xe0010000))
52 return (base
- 0xe0000000)//0x800
54 interrupt_macros
= get_macros("common/interrupt.h")
55 def interrupt_n(name
):
56 return int(interrupt_macros
[name
+ "_INTERRUPT"], 0)
58 version
= get_macros("common/version.h")["VERSION"][1:-1]
65 self
.asmicon
= asmicon
.ASMIcon(sdram_phy
, sdram_geom
, sdram_timing
)
66 asmiport_wb
= self
.asmicon
.hub
.get_port()
67 asmiport_fb
= self
.asmicon
.hub
.get_port(2)
68 self
.asmicon
.finalize()
73 self
.ddrphy
= s6ddrphy
.S6DDRPHY(sdram_geom
.mux_a
, sdram_geom
.bank_a
, sdram_phy
.dfi_d
)
74 self
.dfii
= dfii
.DFIInjector(csr_offset("DFII"),
75 sdram_geom
.mux_a
, sdram_geom
.bank_a
, sdram_phy
.dfi_d
, sdram_phy
.nphases
)
76 self
.dficon0
= dfi
.Interconnect(self
.dfii
.master
, self
.ddrphy
.dfi
)
77 self
.dficon1
= dfi
.Interconnect(self
.asmicon
.dfi
, self
.dfii
.slave
)
82 self
.cpu
= lm32
.LM32()
83 self
.norflash
= norflash
.NorFlash(25, 12)
84 self
.sram
= wishbone
.SRAM(sram_size
)
85 self
.minimac
= minimac3
.MiniMAC(csr_offset("MINIMAC"))
86 self
.wishbone2asmi
= wishbone2asmi
.WB2ASMI(l2_size
//4, asmiport_wb
)
87 self
.wishbone2csr
= wishbone2csr
.WB2CSR()
89 # norflash 0x00000000 (shadow @0x80000000)
90 # SRAM/debug 0x10000000 (shadow @0x90000000)
91 # USB 0x20000000 (shadow @0xa0000000)
92 # Ethernet 0x30000000 (shadow @0xb0000000)
93 # SDRAM 0x40000000 (shadow @0xc0000000)
94 # CSR bridge 0x60000000 (shadow @0xe0000000)
95 self
.wishbonecon
= wishbone
.InterconnectShared(
100 (lambda a
: a
[26:29] == 0, self
.norflash
.bus
),
101 (lambda a
: a
[26:29] == 1, self
.sram
.bus
),
102 (lambda a
: a
[26:29] == 3, self
.minimac
.membus
),
103 (lambda a
: a
[27:29] == 2, self
.wishbone2asmi
.wishbone
),
104 (lambda a
: a
[27:29] == 3, self
.wishbone2csr
.wishbone
)
111 self
.uart
= uart
.UART(csr_offset("UART"), clk_freq
, baud
=115200)
112 self
.identifier
= identifier
.Identifier(csr_offset("ID"), 0x4D31, version
, int(clk_freq
))
113 self
.timer
= timer
.Timer(csr_offset("TIMER0"))
114 self
.fb
= framebuffer
.Framebuffer(csr_offset("FB"), asmiport_fb
)
115 self
.asmiprobe
= asmiprobe
.ASMIprobe(csr_offset("ASMIPROBE"), self
.asmicon
.hub
)
116 self
.csrcon
= csr
.Interconnect(self
.wishbone2csr
.csr
, [
119 self
.identifier
.bank
.bus
,
121 self
.minimac
.bank
.bus
,
123 self
.asmiprobe
.bank
.bus
129 self
.crg
= m1crg
.M1CRG(50*MHz
, clk_freq
)
131 def get_fragment(self
):
136 self
.cpu
.interrupt
[interrupt_n("UART")].eq(self
.uart
.events
.irq
),
137 self
.cpu
.interrupt
[interrupt_n("TIMER0")].eq(self
.timer
.events
.irq
),
138 self
.cpu
.interrupt
[interrupt_n("MINIMAC")].eq(self
.minimac
.events
.irq
),
142 self
.ddrphy
.clk4x_wr_strb
.eq(self
.crg
.clk4x_wr_strb
),
143 self
.ddrphy
.clk4x_rd_strb
.eq(self
.crg
.clk4x_rd_strb
)
145 glue
= Fragment(comb
)
146 return glue
+ autofragment
.from_attributes(self
)