top.py

   1 from migen.fhdl.structure import *
   2 from migen.fhdl import tools, verilog, autofragment
   3 from migen.bus import wishbone, csr, wishbone2csr
   4
   5 from milkymist import m1reset, clkfx, lm32, norflash, uart, sram
   6 import constraints
   7
   8 def get():
   9         MHz = 1000000
  10         clk_freq = 80*MHz
  11         sram_size = 4096 # in bytes
  12
  13         clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
  14         reset0 = m1reset.M1Reset()
  15
  16         cpu0 = lm32.LM32()
  17         norflash0 = norflash.NorFlash(25, 12)
  18         sram0 = sram.SRAM(sram_size//4)
  19         wishbone2csr0 = wishbone2csr.WB2CSR()
  20
  21         # norflash     0x00000000 (shadow @0x80000000)
  22         # SRAM/debug   0x10000000 (shadow @0x90000000)
  23         # USB          0x20000000 (shadow @0xa0000000)
  24         # Ethernet     0x30000000 (shadow @0xb0000000)
  25         # SDRAM        0x40000000 (shadow @0xc0000000)
  26         # CSR bridge   0x60000000 (shadow @0xe0000000)
  27         wishbonecon0 = wishbone.InterconnectShared(
  28                 [
  29                         cpu0.ibus,
  30                         cpu0.dbus
  31                 ], [
  32                         (binc("000"), norflash0.bus),
  33                         (binc("001"), sram0.bus),
  34                         (binc("11"), wishbone2csr0.wishbone)
  35                 ],
  36                 register=True,
  37                 offset=1)
  38
  39         uart0 = uart.UART(0, clk_freq, baud=115200)
  40         csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
  41
  42         interrupts = Fragment([
  43                 cpu0.interrupt[0].eq(uart0.events.irq)
  44         ])
  45
  46         frag = autofragment.from_local() + interrupts
  47         src_verilog, vns = verilog.convert(frag,
  48                 {clkfx_sys.clkin, reset0.trigger_reset},
  49                 name="soc",
  50                 clk_signal=clkfx_sys.clkout,
  51                 rst_signal=reset0.sys_rst,
  52                 return_ns=True)
  53         src_ucf = constraints.get(vns, clkfx_sys, reset0, norflash0, uart0)
  54         return (src_verilog, src_ucf)