top.py

   1 from migen.fhdl import convtools, verilog, autofragment
   2 from migen.bus import wishbone, csr, wishbone2csr
   3 from milkymist import lm32, norflash, uart
   4 import constraints
   5
   6 def Get():
   7         cpu0 = lm32.Inst()
   8         norflash0 = norflash.Inst(25, 12)
   9         wishbone2csr0 = wishbone2csr.Inst()
  10         wishbonecon0 = wishbone.InterconnectShared(
  11                 [cpu0.ibus, cpu0.dbus],
  12                 [(0, norflash0.bus), (3, wishbone2csr0.wishbone)],
  13                 register=True,
  14                 offset=1)
  15         uart0 = uart.Inst(0, 50*1000*1000, baud=115200)
  16         csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bus])
  17
  18         frag = autofragment.FromLocal()
  19         vns = convtools.Namespace()
  20         src_verilog = verilog.Convert(frag, name="soc", ns=vns)
  21         src_ucf = constraints.Get(vns, norflash0, uart0)
  22         return (src_verilog, src_ucf)