top.py

   1 from migen.fhdl.structure import *
   2 from migen.fhdl import convtools, verilog, autofragment
   3 from migen.bus import wishbone, csr, wishbone2csr
   4
   5 from milkymist import m1reset, clkfx, lm32, norflash, uart
   6 import constraints
   7
   8 def get():
   9         MHz = 1000000
  10         clk_freq = 80*MHz
  11
  12         clkfx_sys = clkfx.Inst(50*MHz, clk_freq)
  13         reset0 = m1reset.Inst()
  14
  15         cpu0 = lm32.Inst()
  16         norflash0 = norflash.Inst(25, 12)
  17         wishbone2csr0 = wishbone2csr.Inst()
  18         wishbonecon0 = wishbone.InterconnectShared(
  19                 [cpu0.ibus, cpu0.dbus],
  20                 [(0, norflash0.bus), (3, wishbone2csr0.wishbone)],
  21                 register=True,
  22                 offset=1)
  23         uart0 = uart.Inst(0, clk_freq, baud=115200)
  24         csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
  25
  26         frag = autofragment.from_local()
  27         vns = convtools.Namespace()
  28         src_verilog = verilog.convert(frag,
  29                 {clkfx_sys.clkin, reset0.trigger_reset},
  30                 name="soc",
  31                 clk_signal=clkfx_sys.clkout,
  32                 rst_signal=reset0.sys_rst,
  33                 ns=vns)
  34         src_ucf = constraints.get(vns, clkfx_sys, reset0, norflash0, uart0)
  35         return (src_verilog, src_ucf)