1 from fractions
import Fraction
4 from migen
.fhdl
.structure
import *
5 from migen
.fhdl
import verilog
, autofragment
6 from migen
.bus
import wishbone
, wishbone2asmi
, csr
, wishbone2csr
, dfi
8 from milkymist
import m1crg
, lm32
, norflash
, uart
, sram
, s6ddrphy
, dfii
, asmicon
, \
9 identifier
, timer
, minimac3
, framebuffer
10 from cmacros
import get_macros
11 from constraints
import Constraints
14 clk_freq
= (83 + Fraction(1, 3))*MHz
15 sram_size
= 4096 # in bytes
16 l2_size
= 8192 # in bytes
18 clk_period_ns
= 1000000000/clk_freq
19 def ns(t
, margin
=True):
22 return ceil(t
/clk_period_ns
)
24 sdram_phy
= asmicon
.PhySettings(
30 sdram_geom
= asmicon
.GeomSettings(
35 sdram_timing
= asmicon
.TimingSettings(
39 tREFI
=ns(7800, False),
50 def ddrphy_clocking(crg
, phy
):
58 comb
= [getattr(phy
, name
).eq(getattr(crg
, name
)) for name
in names
]
61 csr_macros
= get_macros("common/csrbase.h")
63 base
= int(csr_macros
[name
+ "_BASE"], 0)
64 assert((base
>= 0xe0000000) and (base
<= 0xe0010000))
65 return (base
- 0xe0000000)//0x800
67 interrupt_macros
= get_macros("common/interrupt.h")
68 def interrupt_n(name
):
69 return int(interrupt_macros
[name
+ "_INTERRUPT"], 0)
71 version
= get_macros("common/version.h")["VERSION"][1:-1]
77 asmicon0
= asmicon
.ASMIcon(sdram_phy
, sdram_geom
, sdram_timing
)
78 asmiport_wb
= asmicon0
.hub
.get_port()
79 asmiport_fb
= asmicon0
.hub
.get_port(2)
85 ddrphy0
= s6ddrphy
.S6DDRPHY(sdram_geom
.mux_a
, sdram_geom
.bank_a
, sdram_phy
.dfi_d
)
86 dfii0
= dfii
.DFIInjector(csr_offset("DFII"),
87 sdram_geom
.mux_a
, sdram_geom
.bank_a
, sdram_phy
.dfi_d
, sdram_phy
.nphases
)
88 dficon0
= dfi
.Interconnect(dfii0
.master
, ddrphy0
.dfi
)
89 dficon1
= dfi
.Interconnect(asmicon0
.dfi
, dfii0
.slave
)
95 norflash0
= norflash
.NorFlash(25, 12)
96 sram0
= sram
.SRAM(sram_size
//4)
97 minimac0
= minimac3
.MiniMAC(csr_offset("MINIMAC"))
98 wishbone2asmi0
= wishbone2asmi
.WB2ASMI(l2_size
//4, asmiport_wb
)
99 wishbone2csr0
= wishbone2csr
.WB2CSR()
101 # norflash 0x00000000 (shadow @0x80000000)
102 # SRAM/debug 0x10000000 (shadow @0x90000000)
103 # USB 0x20000000 (shadow @0xa0000000)
104 # Ethernet 0x30000000 (shadow @0xb0000000)
105 # SDRAM 0x40000000 (shadow @0xc0000000)
106 # CSR bridge 0x60000000 (shadow @0xe0000000)
107 wishbonecon0
= wishbone
.InterconnectShared(
112 (binc("000"), norflash0
.bus
),
113 (binc("001"), sram0
.bus
),
114 (binc("011"), minimac0
.membus
),
115 (binc("10"), wishbone2asmi0
.wishbone
),
116 (binc("11"), wishbone2csr0
.wishbone
)
124 uart0
= uart
.UART(csr_offset("UART"), clk_freq
, baud
=115200)
125 identifier0
= identifier
.Identifier(csr_offset("ID"), 0x4D31, version
, int(clk_freq
))
126 timer0
= timer
.Timer(csr_offset("TIMER0"))
127 fb0
= framebuffer
.Framebuffer(csr_offset("FB"), asmiport_fb
)
128 csrcon0
= csr
.Interconnect(wishbone2csr0
.csr
, [
129 uart0
.bank
.interface
,
130 dfii0
.bank
.interface
,
131 identifier0
.bank
.interface
,
132 timer0
.bank
.interface
,
133 minimac0
.bank
.interface
,
140 interrupts
= Fragment([
141 cpu0
.interrupt
[interrupt_n("UART")].eq(uart0
.events
.irq
),
142 cpu0
.interrupt
[interrupt_n("TIMER0")].eq(timer0
.events
.irq
),
143 cpu0
.interrupt
[interrupt_n("MINIMAC")].eq(minimac0
.events
.irq
)
149 crg0
= m1crg
.M1CRG(50*MHz
, clk_freq
)
151 vga_clocking
= Fragment([
152 fb0
.vga_clk
.eq(crg0
.vga_clk
)
154 frag
= autofragment
.from_local() \
156 + ddrphy_clocking(crg0
, ddrphy0
) \
158 cst
= Constraints(crg0
, norflash0
, uart0
, ddrphy0
, minimac0
, fb0
)
159 src_verilog
, vns
= verilog
.convert(frag
,
162 clk_signal
=crg0
.sys_clk
,
163 rst_signal
=crg0
.sys_rst
,
165 src_ucf
= cst
.get_ucf(vns
)
166 return (src_verilog
, src_ucf
)