1 from fractions
import Fraction
4 from migen
.fhdl
.structure
import *
5 from migen
.fhdl
import verilog
, autofragment
6 from migen
.bus
import wishbone
, wishbone2asmi
, csr
, wishbone2csr
, dfi
8 from milkymist
import m1crg
, lm32
, norflash
, uart
, sram
, s6ddrphy
, dfii
, asmicon
, identifier
, timer
, minimac3
9 from cmacros
import get_macros
10 from constraints
import Constraints
13 clk_freq
= (83 + Fraction(1, 3))*MHz
14 sram_size
= 4096 # in bytes
15 l2_size
= 8192 # in bytes
17 clk_period_ns
= 1000000000/clk_freq
18 def ns(t
, margin
=True):
21 return ceil(t
/clk_period_ns
)
23 sdram_phy
= asmicon
.PhySettings(
29 sdram_geom
= asmicon
.GeomSettings(
34 sdram_timing
= asmicon
.TimingSettings(
38 tREFI
=ns(7800, False),
49 def ddrphy_clocking(crg
, phy
):
57 comb
= [getattr(phy
, name
).eq(getattr(crg
, name
)) for name
in names
]
60 csr_macros
= get_macros("common/csrbase.h")
62 base
= int(csr_macros
[name
+ "_BASE"], 0)
63 assert((base
>= 0xe0000000) and (base
<= 0xe0010000))
64 return (base
- 0xe0000000)//0x800
66 interrupt_macros
= get_macros("common/interrupt.h")
67 def interrupt_n(name
):
68 return int(interrupt_macros
[name
+ "_INTERRUPT"], 0)
70 version
= get_macros("common/version.h")["VERSION"][1:-1]
76 asmicon0
= asmicon
.ASMIcon(sdram_phy
, sdram_geom
, sdram_timing
)
77 asmiport_wb
= asmicon0
.hub
.get_port()
83 ddrphy0
= s6ddrphy
.S6DDRPHY(sdram_geom
.mux_a
, sdram_geom
.bank_a
, sdram_phy
.dfi_d
)
84 dfii0
= dfii
.DFIInjector(csr_offset("DFII"),
85 sdram_geom
.mux_a
, sdram_geom
.bank_a
, sdram_phy
.dfi_d
, sdram_phy
.nphases
)
86 dficon0
= dfi
.Interconnect(dfii0
.master
, ddrphy0
.dfi
)
87 dficon1
= dfi
.Interconnect(asmicon0
.dfi
, dfii0
.slave
)
93 norflash0
= norflash
.NorFlash(25, 12)
94 sram0
= sram
.SRAM(sram_size
//4)
95 minimac0
= minimac3
.MiniMAC(csr_offset("MINIMAC"))
96 wishbone2asmi0
= wishbone2asmi
.WB2ASMI(l2_size
//4, asmiport_wb
)
97 wishbone2csr0
= wishbone2csr
.WB2CSR()
99 # norflash 0x00000000 (shadow @0x80000000)
100 # SRAM/debug 0x10000000 (shadow @0x90000000)
101 # USB 0x20000000 (shadow @0xa0000000)
102 # Ethernet 0x30000000 (shadow @0xb0000000)
103 # SDRAM 0x40000000 (shadow @0xc0000000)
104 # CSR bridge 0x60000000 (shadow @0xe0000000)
105 wishbonecon0
= wishbone
.InterconnectShared(
110 (binc("000"), norflash0
.bus
),
111 (binc("001"), sram0
.bus
),
112 (binc("011"), minimac0
.membus
),
113 (binc("10"), wishbone2asmi0
.wishbone
),
114 (binc("11"), wishbone2csr0
.wishbone
)
122 uart0
= uart
.UART(csr_offset("UART"), clk_freq
, baud
=115200)
123 identifier0
= identifier
.Identifier(csr_offset("ID"), 0x4D31, version
)
124 timer0
= timer
.Timer(csr_offset("TIMER0"))
125 csrcon0
= csr
.Interconnect(wishbone2csr0
.csr
, [
126 uart0
.bank
.interface
,
127 dfii0
.bank
.interface
,
128 identifier0
.bank
.interface
,
129 timer0
.bank
.interface
,
130 minimac0
.bank
.interface
136 interrupts
= Fragment([
137 cpu0
.interrupt
[interrupt_n("UART")].eq(uart0
.events
.irq
),
138 cpu0
.interrupt
[interrupt_n("TIMER0")].eq(timer0
.events
.irq
),
139 cpu0
.interrupt
[interrupt_n("MINIMAC")].eq(minimac0
.events
.irq
)
145 crg0
= m1crg
.M1CRG(50*MHz
, clk_freq
)
147 frag
= autofragment
.from_local() + interrupts
+ ddrphy_clocking(crg0
, ddrphy0
)
148 cst
= Constraints(crg0
, norflash0
, uart0
, ddrphy0
, minimac0
)
149 src_verilog
, vns
= verilog
.convert(frag
,
152 clk_signal
=crg0
.sys_clk
,
153 rst_signal
=crg0
.sys_rst
,
155 src_ucf
= cst
.get_ucf(vns
)
156 return (src_verilog
, src_ucf
)