verilog/generic/asfifo_graycounter.v

   1 /*
   2  * This file is based on "Asynchronous FIFO" by Alex Claros F.,
   3  * itself based on the article "Asynchronous FIFO in Virtex-II FPGAs"
   4  * by Peter Alfke.
   5  */
   6
   7 module asfifo_graycounter #(
   8         parameter width = 2
   9 ) (
  10         output reg [width-1:0] gray_count,
  11         input ce,
  12         input rst,
  13         input clk
  14 );
  15
  16 reg [width-1:0] binary_count;
  17
  18 always @(posedge clk, posedge rst) begin
  19         if(rst) begin
  20                 binary_count <= {width{1'b0}} + 1;
  21                 gray_count <= {width{1'b0}};
  22         end else if(ce) begin
  23                 binary_count <= binary_count + 1;
  24                 gray_count <= {binary_count[width-1],
  25                                 binary_count[width-2:0] ^ binary_count[width-1:1]};
  26         end
  27 end
  28
  29 endmodule