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1 // ==================================================================
2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 // ------------------------------------------------------------------
4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5 // ALL RIGHTS RESERVED
6 // ------------------------------------------------------------------
7 //
8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9 //
10 // Permission:
11 //
12 // Lattice Semiconductor grants permission to use this code
13 // pursuant to the terms of the Lattice Semiconductor Corporation
14 // Open Source License Agreement.
15 //
16 // Disclaimer:
17 //
18 // Lattice Semiconductor provides no warranty regarding the use or
19 // functionality of this code. It is the user's responsibility to
20 // verify the user's design for consistency and functionality through
21 // the use of formal verification methods.
22 //
23 // --------------------------------------------------------------------
24 //
25 // Lattice Semiconductor Corporation
26 // 5555 NE Moore Court
27 // Hillsboro, OR 97214
28 // U.S.A
29 //
30 // TEL: 1-800-Lattice (USA and Canada)
31 // 503-286-8001 (other locations)
32 //
33 // web: http://www.latticesemi.com/
34 // email: techsupport@latticesemi.com
35 //
36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // Project : LatticeMico32
39 // File : lm32_cpu.v
40 // Title : Top-level of CPU.
41 // Dependencies : lm32_include.v
42 //
43 // Version 3.8
44 // 1. Feature: Support for dynamically switching EBA to DEBA via a GPIO.
45 // 2. Bug: EA now reports instruction that caused the data abort, rather than
46 // next instruction.
47 //
48 // Version 3.4
49 // 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were
50 // never serviced.
51 //
52 // Version 3.3
53 // 1. Feature: Support for memory that is tightly coupled to processor core, and
54 // has a single-cycle access latency (same as caches). Instruction port has
55 // access to a dedicated physically-mapped memory. Data port has access to
56 // a dedicated physically-mapped memory. In order to be able to manipulate
57 // values in both these memories via the debugger, these memories also
58 // interface with the data port of LM32.
59 // 2. Feature: Extended Configuration Register
60 // 3. Bug Fix: Removed port names that conflict with keywords reserved in System-
61 // Verilog.
62 //
63 // Version 3.2
64 // 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to
65 // hang. At the same time CPU fails to register data bus error exception. Bug
66 // is caused because (a) data bus error exception occurs after load/store has
67 // passed X stage and next sequential instruction (e.g., brk) is already in X
68 // stage, and (b) data bus error exception had lower priority than, say, brk
69 // exception.
70 // 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to
71 // invalid location, CPU will fail to register data bus error exception. The
72 // solution is to stall scall/eret/bret/brk instructions in D pipeline stage
73 // until load/store has completed.
74 // 3. Feature: Enable precise identification of load/store that causes seg fault.
75 // 4. SYNC resets used for register file when implemented in EBRs.
76 //
77 // Version 3.1
78 // 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR)
79 // instead of distributed memory by enabling the option in LM32 GUI.
80 // 2. Feature: LM32 also adds a static branch predictor to improve branch
81 // performance. All immediate-based forward-pointing branches are predicted
82 // not-taken. All immediate-based backward-pointing branches are predicted taken.
83 //
84 // Version 7.0SP2, 3.0
85 // No Change
86 //
87 // Version 6.1.17
88 // Initial Release
89 // =============================================================================
90
91 `include "lm32_include.v"
92
93 /////////////////////////////////////////////////////
94 // Module interface
95 /////////////////////////////////////////////////////
96
97 module lm32_cpu (
98 // ----- Inputs -------
99 clk_i,
100 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
101 clk_n_i,
102 `endif
103 rst_i,
104 `ifdef CFG_DEBUG_ENABLED
105 `ifdef CFG_ALTERNATE_EBA
106 at_debug,
107 `endif
108 `endif
109 // From external devices
110 `ifdef CFG_INTERRUPTS_ENABLED
111 interrupt,
112 `endif
113 // From user logic
114 `ifdef CFG_USER_ENABLED
115 user_result,
116 user_complete,
117 `endif
118 `ifdef CFG_JTAG_ENABLED
119 // From JTAG
120 jtag_clk,
121 jtag_update,
122 jtag_reg_q,
123 jtag_reg_addr_q,
124 `endif
125 `ifdef CFG_EXTERNAL_BREAK_ENABLED
126 ext_break,
127 `endif
128 `ifdef CFG_IWB_ENABLED
129 // Instruction Wishbone master
130 I_DAT_I,
131 I_ACK_I,
132 I_ERR_I,
133 I_RTY_I,
134 `endif
135 // Data Wishbone master
136 D_DAT_I,
137 D_ACK_I,
138 D_ERR_I,
139 D_RTY_I,
140 // ----- Outputs -------
141 `ifdef CFG_TRACE_ENABLED
142 trace_pc,
143 trace_pc_valid,
144 trace_exception,
145 trace_eid,
146 trace_eret,
147 `ifdef CFG_DEBUG_ENABLED
148 trace_bret,
149 `endif
150 `endif
151 `ifdef CFG_JTAG_ENABLED
152 jtag_reg_d,
153 jtag_reg_addr_d,
154 `endif
155 `ifdef CFG_USER_ENABLED
156 user_valid,
157 user_opcode,
158 user_operand_0,
159 user_operand_1,
160 `endif
161 `ifdef CFG_IWB_ENABLED
162 // Instruction Wishbone master
163 I_DAT_O,
164 I_ADR_O,
165 I_CYC_O,
166 I_SEL_O,
167 I_STB_O,
168 I_WE_O,
169 I_CTI_O,
170 I_LOCK_O,
171 I_BTE_O,
172 `endif
173 // Data Wishbone master
174 D_DAT_O,
175 D_ADR_O,
176 D_CYC_O,
177 D_SEL_O,
178 D_STB_O,
179 D_WE_O,
180 D_CTI_O,
181 D_LOCK_O,
182 D_BTE_O
183 );
184
185 /////////////////////////////////////////////////////
186 // Parameters
187 /////////////////////////////////////////////////////
188
189 parameter eba_reset = `CFG_EBA_RESET; // Reset value for EBA CSR
190 `ifdef CFG_DEBUG_ENABLED
191 parameter deba_reset = `CFG_DEBA_RESET; // Reset value for DEBA CSR
192 `endif
193
194 `ifdef CFG_ICACHE_ENABLED
195 parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways)
196 parameter icache_sets = `CFG_ICACHE_SETS; // Number of sets
197 parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE; // Number of bytes per cache line
198 parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS; // Base address of cachable memory
199 parameter icache_limit = `CFG_ICACHE_LIMIT; // Limit (highest address) of cachable memory
200 `else
201 parameter icache_associativity = 1;
202 parameter icache_sets = 512;
203 parameter icache_bytes_per_line = 16;
204 parameter icache_base_address = 0;
205 parameter icache_limit = 0;
206 `endif
207
208 `ifdef CFG_DCACHE_ENABLED
209 parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways)
210 parameter dcache_sets = `CFG_DCACHE_SETS; // Number of sets
211 parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE; // Number of bytes per cache line
212 parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS; // Base address of cachable memory
213 parameter dcache_limit = `CFG_DCACHE_LIMIT; // Limit (highest address) of cachable memory
214 `else
215 parameter dcache_associativity = 1;
216 parameter dcache_sets = 512;
217 parameter dcache_bytes_per_line = 16;
218 parameter dcache_base_address = 0;
219 parameter dcache_limit = 0;
220 `endif
221
222 `ifdef CFG_DEBUG_ENABLED
223 parameter watchpoints = `CFG_WATCHPOINTS; // Number of h/w watchpoint CSRs
224 `else
225 parameter watchpoints = 0;
226 `endif
227 `ifdef CFG_ROM_DEBUG_ENABLED
228 parameter breakpoints = `CFG_BREAKPOINTS; // Number of h/w breakpoint CSRs
229 `else
230 parameter breakpoints = 0;
231 `endif
232
233 `ifdef CFG_INTERRUPTS_ENABLED
234 parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
235 `else
236 parameter interrupts = 0;
237 `endif
238
239 /////////////////////////////////////////////////////
240 // Inputs
241 /////////////////////////////////////////////////////
242
243 input clk_i; // Clock
244 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
245 input clk_n_i; // Inverted clock
246 `endif
247 input rst_i; // Reset
248
249 `ifdef CFG_DEBUG_ENABLED
250 `ifdef CFG_ALTERNATE_EBA
251 input at_debug; // GPIO input that maps EBA to DEBA
252 `endif
253 `endif
254
255 `ifdef CFG_INTERRUPTS_ENABLED
256 input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins
257 `endif
258
259 `ifdef CFG_USER_ENABLED
260 input [`LM32_WORD_RNG] user_result; // User-defined instruction result
261 input user_complete; // User-defined instruction execution is complete
262 `endif
263
264 `ifdef CFG_JTAG_ENABLED
265 input jtag_clk; // JTAG clock
266 input jtag_update; // JTAG state machine is in data register update state
267 input [`LM32_BYTE_RNG] jtag_reg_q;
268 input [2:0] jtag_reg_addr_q;
269 `endif
270
271 `ifdef CFG_IWB_ENABLED
272 input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
273 input I_ACK_I; // Instruction Wishbone interface acknowledgement
274 input I_ERR_I; // Instruction Wishbone interface error
275 input I_RTY_I; // Instruction Wishbone interface retry
276 `endif
277
278 input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
279 input D_ACK_I; // Data Wishbone interface acknowledgement
280 input D_ERR_I; // Data Wishbone interface error
281 input D_RTY_I; // Data Wishbone interface retry
282
283 `ifdef CFG_EXTERNAL_BREAK_ENABLED
284 input ext_break;
285 `endif
286
287 /////////////////////////////////////////////////////
288 // Outputs
289 /////////////////////////////////////////////////////
290
291 `ifdef CFG_TRACE_ENABLED
292 output [`LM32_PC_RNG] trace_pc; // PC to trace
293 reg [`LM32_PC_RNG] trace_pc;
294 output trace_pc_valid; // Indicates that a new trace PC is valid
295 reg trace_pc_valid;
296 output trace_exception; // Indicates an exception has occured
297 reg trace_exception;
298 output [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
299 reg [`LM32_EID_RNG] trace_eid;
300 output trace_eret; // Indicates an eret instruction has been executed
301 reg trace_eret;
302 `ifdef CFG_DEBUG_ENABLED
303 output trace_bret; // Indicates a bret instruction has been executed
304 reg trace_bret;
305 `endif
306 `endif
307
308 `ifdef CFG_JTAG_ENABLED
309 output [`LM32_BYTE_RNG] jtag_reg_d;
310 wire [`LM32_BYTE_RNG] jtag_reg_d;
311 output [2:0] jtag_reg_addr_d;
312 wire [2:0] jtag_reg_addr_d;
313 `endif
314
315 `ifdef CFG_USER_ENABLED
316 output user_valid; // Indicates if user_opcode is valid
317 wire user_valid;
318 output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
319 reg [`LM32_USER_OPCODE_RNG] user_opcode;
320 output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
321 wire [`LM32_WORD_RNG] user_operand_0;
322 output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
323 wire [`LM32_WORD_RNG] user_operand_1;
324 `endif
325
326 `ifdef CFG_IWB_ENABLED
327 output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
328 wire [`LM32_WORD_RNG] I_DAT_O;
329 output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
330 wire [`LM32_WORD_RNG] I_ADR_O;
331 output I_CYC_O; // Instruction Wishbone interface cycle
332 wire I_CYC_O;
333 output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
334 wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
335 output I_STB_O; // Instruction Wishbone interface strobe
336 wire I_STB_O;
337 output I_WE_O; // Instruction Wishbone interface write enable
338 wire I_WE_O;
339 output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
340 wire [`LM32_CTYPE_RNG] I_CTI_O;
341 output I_LOCK_O; // Instruction Wishbone interface lock bus
342 wire I_LOCK_O;
343 output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
344 wire [`LM32_BTYPE_RNG] I_BTE_O;
345 `endif
346
347 output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
348 wire [`LM32_WORD_RNG] D_DAT_O;
349 output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
350 wire [`LM32_WORD_RNG] D_ADR_O;
351 output D_CYC_O; // Data Wishbone interface cycle
352 wire D_CYC_O;
353 output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
354 wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
355 output D_STB_O; // Data Wishbone interface strobe
356 wire D_STB_O;
357 output D_WE_O; // Data Wishbone interface write enable
358 wire D_WE_O;
359 output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
360 wire [`LM32_CTYPE_RNG] D_CTI_O;
361 output D_LOCK_O; // Date Wishbone interface lock bus
362 wire D_LOCK_O;
363 output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
364 wire [`LM32_BTYPE_RNG] D_BTE_O;
365
366 /////////////////////////////////////////////////////
367 // Internal nets and registers
368 /////////////////////////////////////////////////////
369
370 // Pipeline registers
371
372 `ifdef LM32_CACHE_ENABLED
373 reg valid_a; // Instruction in A stage is valid
374 `endif
375 reg valid_f; // Instruction in F stage is valid
376 reg valid_d; // Instruction in D stage is valid
377 reg valid_x; // Instruction in X stage is valid
378 reg valid_m; // Instruction in M stage is valid
379 reg valid_w; // Instruction in W stage is valid
380
381 wire q_x;
382 wire [`LM32_WORD_RNG] immediate_d; // Immediate operand
383 wire load_d; // Indicates a load instruction
384 reg load_x;
385 reg load_m;
386 wire load_q_x;
387 wire store_q_x;
388 wire store_d; // Indicates a store instruction
389 reg store_x;
390 reg store_m;
391 wire [`LM32_SIZE_RNG] size_d; // Size of load/store (byte, hword, word)
392 reg [`LM32_SIZE_RNG] size_x;
393 wire branch_d; // Indicates a branch instruction
394 wire branch_predict_d; // Indicates a branch is predicted
395 wire branch_predict_taken_d; // Indicates a branch is predicted taken
396 wire [`LM32_PC_RNG] branch_predict_address_d; // Address to which predicted branch jumps
397 wire [`LM32_PC_RNG] branch_target_d;
398 wire bi_unconditional;
399 wire bi_conditional;
400 reg branch_x;
401 reg branch_predict_x;
402 reg branch_predict_taken_x;
403 reg branch_m;
404 reg branch_predict_m;
405 reg branch_predict_taken_m;
406 wire branch_mispredict_taken_m; // Indicates a branch was mispredicted as taken
407 wire branch_flushX_m; // Indicates that instruction in X stage must be squashed
408 wire branch_reg_d; // Branch to register or immediate
409 wire [`LM32_PC_RNG] branch_offset_d; // Branch offset for immediate branches
410 reg [`LM32_PC_RNG] branch_target_x; // Address to branch to
411 reg [`LM32_PC_RNG] branch_target_m;
412 wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
413 wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
414
415 wire x_result_sel_csr_d; // Select X stage result from CSRs
416 reg x_result_sel_csr_x;
417 `ifdef LM32_MC_ARITHMETIC_ENABLED
418 wire x_result_sel_mc_arith_d; // Select X stage result from multi-cycle arithmetic unit
419 reg x_result_sel_mc_arith_x;
420 `endif
421 `ifdef LM32_NO_BARREL_SHIFT
422 wire x_result_sel_shift_d; // Select X stage result from shifter
423 reg x_result_sel_shift_x;
424 `endif
425 `ifdef CFG_SIGN_EXTEND_ENABLED
426 wire x_result_sel_sext_d; // Select X stage result from sign-extend logic
427 reg x_result_sel_sext_x;
428 `endif
429 wire x_result_sel_logic_d; // Select X stage result from logic op unit
430 reg x_result_sel_logic_x;
431 `ifdef CFG_USER_ENABLED
432 wire x_result_sel_user_d; // Select X stage result from user-defined logic
433 reg x_result_sel_user_x;
434 `endif
435 wire x_result_sel_add_d; // Select X stage result from adder
436 reg x_result_sel_add_x;
437 wire m_result_sel_compare_d; // Select M stage result from comparison logic
438 reg m_result_sel_compare_x;
439 reg m_result_sel_compare_m;
440 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
441 wire m_result_sel_shift_d; // Select M stage result from shifter
442 reg m_result_sel_shift_x;
443 reg m_result_sel_shift_m;
444 `endif
445 wire w_result_sel_load_d; // Select W stage result from load/store unit
446 reg w_result_sel_load_x;
447 reg w_result_sel_load_m;
448 reg w_result_sel_load_w;
449 `ifdef CFG_PL_MULTIPLY_ENABLED
450 wire w_result_sel_mul_d; // Select W stage result from multiplier
451 reg w_result_sel_mul_x;
452 reg w_result_sel_mul_m;
453 reg w_result_sel_mul_w;
454 `endif
455 wire x_bypass_enable_d; // Whether result is bypassable in X stage
456 reg x_bypass_enable_x;
457 wire m_bypass_enable_d; // Whether result is bypassable in M stage
458 reg m_bypass_enable_x;
459 reg m_bypass_enable_m;
460 wire sign_extend_d; // Whether to sign-extend or zero-extend
461 reg sign_extend_x;
462 wire write_enable_d; // Register file write enable
463 reg write_enable_x;
464 wire write_enable_q_x;
465 reg write_enable_m;
466 wire write_enable_q_m;
467 reg write_enable_w;
468 wire write_enable_q_w;
469 wire read_enable_0_d; // Register file read enable 0
470 wire [`LM32_REG_IDX_RNG] read_idx_0_d; // Register file read index 0
471 wire read_enable_1_d; // Register file read enable 1
472 wire [`LM32_REG_IDX_RNG] read_idx_1_d; // Register file read index 1
473 wire [`LM32_REG_IDX_RNG] write_idx_d; // Register file write index
474 reg [`LM32_REG_IDX_RNG] write_idx_x;
475 reg [`LM32_REG_IDX_RNG] write_idx_m;
476 reg [`LM32_REG_IDX_RNG] write_idx_w;
477 wire [`LM32_CSR_RNG] csr_d; // CSR read/write index
478 reg [`LM32_CSR_RNG] csr_x;
479 wire [`LM32_CONDITION_RNG] condition_d; // Branch condition
480 reg [`LM32_CONDITION_RNG] condition_x;
481 `ifdef CFG_DEBUG_ENABLED
482 wire break_d; // Indicates a break instruction
483 reg break_x;
484 `endif
485 wire scall_d; // Indicates a scall instruction
486 reg scall_x;
487 wire eret_d; // Indicates an eret instruction
488 reg eret_x;
489 wire eret_q_x;
490 reg eret_m;
491 `ifdef CFG_TRACE_ENABLED
492 reg eret_w;
493 `endif
494 `ifdef CFG_DEBUG_ENABLED
495 wire bret_d; // Indicates a bret instruction
496 reg bret_x;
497 wire bret_q_x;
498 reg bret_m;
499 `ifdef CFG_TRACE_ENABLED
500 reg bret_w;
501 `endif
502 `endif
503 wire csr_write_enable_d; // CSR write enable
504 reg csr_write_enable_x;
505 wire csr_write_enable_q_x;
506 `ifdef CFG_USER_ENABLED
507 wire [`LM32_USER_OPCODE_RNG] user_opcode_d; // User-defined instruction opcode
508 `endif
509
510 `ifdef CFG_BUS_ERRORS_ENABLED
511 wire bus_error_d; // Indicates an bus error occured while fetching the instruction in this pipeline stage
512 reg bus_error_x;
513 reg data_bus_error_exception_m;
514 reg [`LM32_PC_RNG] memop_pc_w;
515 `endif
516
517 reg [`LM32_WORD_RNG] d_result_0; // Result of instruction in D stage (operand 0)
518 reg [`LM32_WORD_RNG] d_result_1; // Result of instruction in D stage (operand 1)
519 reg [`LM32_WORD_RNG] x_result; // Result of instruction in X stage
520 reg [`LM32_WORD_RNG] m_result; // Result of instruction in M stage
521 reg [`LM32_WORD_RNG] w_result; // Result of instruction in W stage
522
523 reg [`LM32_WORD_RNG] operand_0_x; // Operand 0 for X stage instruction
524 reg [`LM32_WORD_RNG] operand_1_x; // Operand 1 for X stage instruction
525 reg [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
526 reg [`LM32_WORD_RNG] operand_m; // Operand for M stage instruction
527 reg [`LM32_WORD_RNG] operand_w; // Operand for W stage instruction
528
529 // To/from register file
530 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
531 reg [`LM32_WORD_RNG] reg_data_live_0;
532 reg [`LM32_WORD_RNG] reg_data_live_1;
533 reg use_buf; // Whether to use reg_data_live or reg_data_buf
534 reg [`LM32_WORD_RNG] reg_data_buf_0;
535 reg [`LM32_WORD_RNG] reg_data_buf_1;
536 `endif
537 `ifdef LM32_EBR_REGISTER_FILE
538 `else
539 reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1]; // Register file
540 `endif
541 wire [`LM32_WORD_RNG] reg_data_0; // Register file read port 0 data
542 wire [`LM32_WORD_RNG] reg_data_1; // Register file read port 1 data
543 reg [`LM32_WORD_RNG] bypass_data_0; // Register value 0 after bypassing
544 reg [`LM32_WORD_RNG] bypass_data_1; // Register value 1 after bypassing
545 wire reg_write_enable_q_w;
546
547 reg interlock; // Indicates pipeline should be stalled because of a read-after-write hazzard
548
549 wire stall_a; // Stall instruction in A pipeline stage
550 wire stall_f; // Stall instruction in F pipeline stage
551 wire stall_d; // Stall instruction in D pipeline stage
552 wire stall_x; // Stall instruction in X pipeline stage
553 wire stall_m; // Stall instruction in M pipeline stage
554
555 // To/from adder
556 wire adder_op_d; // Whether to add or subtract
557 reg adder_op_x;
558 reg adder_op_x_n; // Inverted version of adder_op_x
559 wire [`LM32_WORD_RNG] adder_result_x; // Result from adder
560 wire adder_overflow_x; // Whether a signed overflow occured
561 wire adder_carry_n_x; // Whether a carry was generated
562
563 // To/from logical operations unit
564 wire [`LM32_LOGIC_OP_RNG] logic_op_d; // Which operation to perform
565 reg [`LM32_LOGIC_OP_RNG] logic_op_x;
566 wire [`LM32_WORD_RNG] logic_result_x; // Result of logical operation
567
568 `ifdef CFG_SIGN_EXTEND_ENABLED
569 // From sign-extension unit
570 wire [`LM32_WORD_RNG] sextb_result_x; // Result of byte sign-extension
571 wire [`LM32_WORD_RNG] sexth_result_x; // Result of half-word sign-extenstion
572 wire [`LM32_WORD_RNG] sext_result_x; // Result of sign-extension specified by instruction
573 `endif
574
575 // To/from shifter
576 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
577 `ifdef CFG_ROTATE_ENABLED
578 wire rotate_d; // Whether we should rotate or shift
579 reg rotate_x;
580 `endif
581 wire direction_d; // Which direction to shift in
582 reg direction_x;
583 wire [`LM32_WORD_RNG] shifter_result_m; // Result of shifter
584 `endif
585 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
586 wire shift_left_d; // Indicates whether to perform a left shift or not
587 wire shift_left_q_d;
588 wire shift_right_d; // Indicates whether to perform a right shift or not
589 wire shift_right_q_d;
590 `endif
591 `ifdef LM32_NO_BARREL_SHIFT
592 wire [`LM32_WORD_RNG] shifter_result_x; // Result of single-bit right shifter
593 `endif
594
595 // To/from multiplier
596 `ifdef LM32_MULTIPLY_ENABLED
597 wire [`LM32_WORD_RNG] multiplier_result_w; // Result from multiplier
598 `endif
599 `ifdef CFG_MC_MULTIPLY_ENABLED
600 wire multiply_d; // Indicates whether to perform a multiply or not
601 wire multiply_q_d;
602 `endif
603
604 // To/from divider
605 `ifdef CFG_MC_DIVIDE_ENABLED
606 wire divide_d; // Indicates whether to perform a divider or not
607 wire divide_q_d;
608 wire modulus_d;
609 wire modulus_q_d;
610 wire divide_by_zero_x; // Indicates an attempt was made to divide by zero
611 `endif
612
613 // To from multi-cycle arithmetic unit
614 `ifdef LM32_MC_ARITHMETIC_ENABLED
615 wire mc_stall_request_x; // Multi-cycle arithmetic unit stall request
616 wire [`LM32_WORD_RNG] mc_result_x;
617 `endif
618
619 // From CSRs
620 `ifdef CFG_INTERRUPTS_ENABLED
621 wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
622 `endif
623 wire [`LM32_WORD_RNG] cfg; // Configuration CSR
624 wire [`LM32_WORD_RNG] cfg2; // Extended Configuration CSR
625 `ifdef CFG_CYCLE_COUNTER_ENABLED
626 reg [`LM32_WORD_RNG] cc; // Cycle counter CSR
627 `endif
628 reg [`LM32_WORD_RNG] csr_read_data_x; // Data read from CSRs
629
630 // To/from instruction unit
631 wire [`LM32_PC_RNG] pc_f; // PC of instruction in F stage
632 wire [`LM32_PC_RNG] pc_d; // PC of instruction in D stage
633 wire [`LM32_PC_RNG] pc_x; // PC of instruction in X stage
634 wire [`LM32_PC_RNG] pc_m; // PC of instruction in M stage
635 wire [`LM32_PC_RNG] pc_w; // PC of instruction in W stage
636 `ifdef CFG_TRACE_ENABLED
637 reg [`LM32_PC_RNG] pc_c; // PC of last commited instruction
638 `endif
639 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
640 wire [`LM32_INSTRUCTION_RNG] instruction_f; // Instruction in F stage
641 `endif
642 //pragma attribute instruction_d preserve_signal true
643 //pragma attribute instruction_d preserve_driver true
644 wire [`LM32_INSTRUCTION_RNG] instruction_d; // Instruction in D stage
645 `ifdef CFG_ICACHE_ENABLED
646 wire iflush; // Flush instruction cache
647 wire icache_stall_request; // Stall pipeline because instruction cache is busy
648 wire icache_restart_request; // Restart instruction that caused an instruction cache miss
649 wire icache_refill_request; // Request to refill instruction cache
650 wire icache_refilling; // Indicates the instruction cache is being refilled
651 `endif
652 `ifdef CFG_IROM_ENABLED
653 wire [`LM32_WORD_RNG] irom_store_data_m; // Store data to instruction ROM
654 wire [`LM32_WORD_RNG] irom_address_xm; // Address to instruction ROM from load-store unit
655 wire [`LM32_WORD_RNG] irom_data_m; // Load data from instruction ROM
656 wire irom_we_xm; // Indicates data needs to be written to instruction ROM
657 wire irom_stall_request_x; // Indicates D stage needs to be stalled on a store to instruction ROM
658 `endif
659
660 // To/from load/store unit
661 `ifdef CFG_DCACHE_ENABLED
662 wire dflush_x; // Flush data cache
663 reg dflush_m;
664 wire dcache_stall_request; // Stall pipeline because data cache is busy
665 wire dcache_restart_request; // Restart instruction that caused a data cache miss
666 wire dcache_refill_request; // Request to refill data cache
667 wire dcache_refilling; // Indicates the data cache is being refilled
668 `endif
669 wire [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
670 wire stall_wb_load; // Stall pipeline because of a load via the data Wishbone interface
671
672 // To/from JTAG interface
673 `ifdef CFG_JTAG_ENABLED
674 `ifdef CFG_JTAG_UART_ENABLED
675 wire [`LM32_WORD_RNG] jtx_csr_read_data; // Read data for JTX CSR
676 wire [`LM32_WORD_RNG] jrx_csr_read_data; // Read data for JRX CSR
677 `endif
678 `ifdef CFG_HW_DEBUG_ENABLED
679 wire jtag_csr_write_enable; // Debugger CSR write enable
680 wire [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
681 wire [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
682 wire jtag_read_enable;
683 wire [`LM32_BYTE_RNG] jtag_read_data;
684 wire jtag_write_enable;
685 wire [`LM32_BYTE_RNG] jtag_write_data;
686 wire [`LM32_WORD_RNG] jtag_address;
687 wire jtag_access_complete;
688 `endif
689 `ifdef CFG_DEBUG_ENABLED
690 wire jtag_break; // Request from debugger to raise a breakpoint
691 `endif
692 `endif
693
694 // Hazzard detection
695 wire raw_x_0; // RAW hazzard between instruction in X stage and read port 0
696 wire raw_x_1; // RAW hazzard between instruction in X stage and read port 1
697 wire raw_m_0; // RAW hazzard between instruction in M stage and read port 0
698 wire raw_m_1; // RAW hazzard between instruction in M stage and read port 1
699 wire raw_w_0; // RAW hazzard between instruction in W stage and read port 0
700 wire raw_w_1; // RAW hazzard between instruction in W stage and read port 1
701
702 // Control flow
703 wire cmp_zero; // Result of comparison is zero
704 wire cmp_negative; // Result of comparison is negative
705 wire cmp_overflow; // Comparison produced an overflow
706 wire cmp_carry_n; // Comparison produced a carry, inverted
707 reg condition_met_x; // Condition of branch instruction is met
708 reg condition_met_m;
709 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
710 wire branch_taken_x; // Branch is taken in X stage
711 `endif
712 wire branch_taken_m; // Branch is taken in M stage
713
714 wire kill_f; // Kill instruction in F stage
715 wire kill_d; // Kill instruction in D stage
716 wire kill_x; // Kill instruction in X stage
717 wire kill_m; // Kill instruction in M stage
718 wire kill_w; // Kill instruction in W stage
719
720 reg [`LM32_PC_WIDTH+2-1:8] eba; // Exception Base Address (EBA) CSR
721 `ifdef CFG_DEBUG_ENABLED
722 reg [`LM32_PC_WIDTH+2-1:8] deba; // Debug Exception Base Address (DEBA) CSR
723 `endif
724 reg [`LM32_EID_RNG] eid_x; // Exception ID in X stage
725 `ifdef CFG_TRACE_ENABLED
726 reg [`LM32_EID_RNG] eid_m; // Exception ID in M stage
727 reg [`LM32_EID_RNG] eid_w; // Exception ID in W stage
728 `endif
729
730 `ifdef CFG_DEBUG_ENABLED
731 `ifdef LM32_SINGLE_STEP_ENABLED
732 wire dc_ss; // Is single-step enabled
733 `endif
734 wire dc_re; // Remap all exceptions
735 wire exception_x; // An exception occured in the X stage
736 reg exception_m; // An instruction that caused an exception is in the M stage
737 wire debug_exception_x; // Indicates if a debug exception has occured
738 reg debug_exception_m;
739 reg debug_exception_w;
740 wire debug_exception_q_w;
741 wire non_debug_exception_x; // Indicates if a non debug exception has occured
742 reg non_debug_exception_m;
743 reg non_debug_exception_w;
744 wire non_debug_exception_q_w;
745 `else
746 wire exception_x; // Indicates if a debug exception has occured
747 reg exception_m;
748 reg exception_w;
749 wire exception_q_w;
750 `endif
751
752 `ifdef CFG_DEBUG_ENABLED
753 wire reset_exception; // Indicates if a reset exception has occured
754 `endif
755 `ifdef CFG_INTERRUPTS_ENABLED
756 wire interrupt_exception; // Indicates if an interrupt exception has occured
757 `endif
758 `ifdef CFG_DEBUG_ENABLED
759 wire breakpoint_exception; // Indicates if a breakpoint exception has occured
760 wire watchpoint_exception; // Indicates if a watchpoint exception has occured
761 `endif
762 `ifdef CFG_BUS_ERRORS_ENABLED
763 wire instruction_bus_error_exception; // Indicates if an instruction bus error exception has occured
764 wire data_bus_error_exception; // Indicates if a data bus error exception has occured
765 `endif
766 `ifdef CFG_MC_DIVIDE_ENABLED
767 wire divide_by_zero_exception; // Indicates if a divide by zero exception has occured
768 `endif
769 wire system_call_exception; // Indicates if a system call exception has occured
770
771 `ifdef CFG_BUS_ERRORS_ENABLED
772 reg data_bus_error_seen; // Indicates if a data bus error was seen
773 `endif
774
775 `ifdef CFG_EXTERNAL_BREAK_ENABLED
776 reg ext_break_r;
777 `endif
778
779 /////////////////////////////////////////////////////
780 // Functions
781 /////////////////////////////////////////////////////
782
783 `include "lm32_functions.v"
784
785 /////////////////////////////////////////////////////
786 // Instantiations
787 /////////////////////////////////////////////////////
788
789 // Instruction unit
790 lm32_instruction_unit #(
791 .associativity (icache_associativity),
792 .sets (icache_sets),
793 .bytes_per_line (icache_bytes_per_line),
794 .base_address (icache_base_address),
795 .limit (icache_limit)
796 ) instruction_unit (
797 // ----- Inputs -------
798 .clk_i (clk_i),
799 .rst_i (rst_i),
800 `ifdef CFG_DEBUG_ENABLED
801 `ifdef CFG_ALTERNATE_EBA
802 .at_debug (at_debug),
803 `endif
804 `endif
805 // From pipeline
806 .stall_a (stall_a),
807 .stall_f (stall_f),
808 .stall_d (stall_d),
809 .stall_x (stall_x),
810 .stall_m (stall_m),
811 .valid_f (valid_f),
812 .valid_d (valid_d),
813 .kill_f (kill_f),
814 .branch_predict_taken_d (branch_predict_taken_d),
815 .branch_predict_address_d (branch_predict_address_d),
816 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
817 .branch_taken_x (branch_taken_x),
818 .branch_target_x (branch_target_x),
819 `endif
820 .exception_m (exception_m),
821 .branch_taken_m (branch_taken_m),
822 .branch_mispredict_taken_m (branch_mispredict_taken_m),
823 .branch_target_m (branch_target_m),
824 `ifdef CFG_ICACHE_ENABLED
825 .iflush (iflush),
826 `endif
827 `ifdef CFG_IROM_ENABLED
828 .irom_store_data_m (irom_store_data_m),
829 .irom_address_xm (irom_address_xm),
830 .irom_we_xm (irom_we_xm),
831 `endif
832 `ifdef CFG_DCACHE_ENABLED
833 .dcache_restart_request (dcache_restart_request),
834 .dcache_refill_request (dcache_refill_request),
835 .dcache_refilling (dcache_refilling),
836 `endif
837 `ifdef CFG_IWB_ENABLED
838 // From Wishbone
839 .i_dat_i (I_DAT_I),
840 .i_ack_i (I_ACK_I),
841 .i_err_i (I_ERR_I),
842 `endif
843 `ifdef CFG_HW_DEBUG_ENABLED
844 .jtag_read_enable (jtag_read_enable),
845 .jtag_write_enable (jtag_write_enable),
846 .jtag_write_data (jtag_write_data),
847 .jtag_address (jtag_address),
848 `endif
849 // ----- Outputs -------
850 // To pipeline
851 .pc_f (pc_f),
852 .pc_d (pc_d),
853 .pc_x (pc_x),
854 .pc_m (pc_m),
855 .pc_w (pc_w),
856 `ifdef CFG_ICACHE_ENABLED
857 .icache_stall_request (icache_stall_request),
858 .icache_restart_request (icache_restart_request),
859 .icache_refill_request (icache_refill_request),
860 .icache_refilling (icache_refilling),
861 `endif
862 `ifdef CFG_IROM_ENABLED
863 .irom_data_m (irom_data_m),
864 `endif
865 `ifdef CFG_IWB_ENABLED
866 // To Wishbone
867 .i_dat_o (I_DAT_O),
868 .i_adr_o (I_ADR_O),
869 .i_cyc_o (I_CYC_O),
870 .i_sel_o (I_SEL_O),
871 .i_stb_o (I_STB_O),
872 .i_we_o (I_WE_O),
873 .i_cti_o (I_CTI_O),
874 .i_lock_o (I_LOCK_O),
875 .i_bte_o (I_BTE_O),
876 `endif
877 `ifdef CFG_HW_DEBUG_ENABLED
878 .jtag_read_data (jtag_read_data),
879 .jtag_access_complete (jtag_access_complete),
880 `endif
881 `ifdef CFG_BUS_ERRORS_ENABLED
882 .bus_error_d (bus_error_d),
883 `endif
884 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
885 .instruction_f (instruction_f),
886 `endif
887 .instruction_d (instruction_d)
888 );
889
890 // Instruction decoder
891 lm32_decoder decoder (
892 // ----- Inputs -------
893 .instruction (instruction_d),
894 // ----- Outputs -------
895 .d_result_sel_0 (d_result_sel_0_d),
896 .d_result_sel_1 (d_result_sel_1_d),
897 .x_result_sel_csr (x_result_sel_csr_d),
898 `ifdef LM32_MC_ARITHMETIC_ENABLED
899 .x_result_sel_mc_arith (x_result_sel_mc_arith_d),
900 `endif
901 `ifdef LM32_NO_BARREL_SHIFT
902 .x_result_sel_shift (x_result_sel_shift_d),
903 `endif
904 `ifdef CFG_SIGN_EXTEND_ENABLED
905 .x_result_sel_sext (x_result_sel_sext_d),
906 `endif
907 .x_result_sel_logic (x_result_sel_logic_d),
908 `ifdef CFG_USER_ENABLED
909 .x_result_sel_user (x_result_sel_user_d),
910 `endif
911 .x_result_sel_add (x_result_sel_add_d),
912 .m_result_sel_compare (m_result_sel_compare_d),
913 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
914 .m_result_sel_shift (m_result_sel_shift_d),
915 `endif
916 .w_result_sel_load (w_result_sel_load_d),
917 `ifdef CFG_PL_MULTIPLY_ENABLED
918 .w_result_sel_mul (w_result_sel_mul_d),
919 `endif
920 .x_bypass_enable (x_bypass_enable_d),
921 .m_bypass_enable (m_bypass_enable_d),
922 .read_enable_0 (read_enable_0_d),
923 .read_idx_0 (read_idx_0_d),
924 .read_enable_1 (read_enable_1_d),
925 .read_idx_1 (read_idx_1_d),
926 .write_enable (write_enable_d),
927 .write_idx (write_idx_d),
928 .immediate (immediate_d),
929 .branch_offset (branch_offset_d),
930 .load (load_d),
931 .store (store_d),
932 .size (size_d),
933 .sign_extend (sign_extend_d),
934 .adder_op (adder_op_d),
935 .logic_op (logic_op_d),
936 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
937 .direction (direction_d),
938 `endif
939 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
940 .shift_left (shift_left_d),
941 .shift_right (shift_right_d),
942 `endif
943 `ifdef CFG_MC_MULTIPLY_ENABLED
944 .multiply (multiply_d),
945 `endif
946 `ifdef CFG_MC_DIVIDE_ENABLED
947 .divide (divide_d),
948 .modulus (modulus_d),
949 `endif
950 .branch (branch_d),
951 .bi_unconditional (bi_unconditional),
952 .bi_conditional (bi_conditional),
953 .branch_reg (branch_reg_d),
954 .condition (condition_d),
955 `ifdef CFG_DEBUG_ENABLED
956 .break_opcode (break_d),
957 `endif
958 .scall (scall_d),
959 .eret (eret_d),
960 `ifdef CFG_DEBUG_ENABLED
961 .bret (bret_d),
962 `endif
963 `ifdef CFG_USER_ENABLED
964 .user_opcode (user_opcode_d),
965 `endif
966 .csr_write_enable (csr_write_enable_d)
967 );
968
969 // Load/store unit
970 lm32_load_store_unit #(
971 .associativity (dcache_associativity),
972 .sets (dcache_sets),
973 .bytes_per_line (dcache_bytes_per_line),
974 .base_address (dcache_base_address),
975 .limit (dcache_limit)
976 ) load_store_unit (
977 // ----- Inputs -------
978 .clk_i (clk_i),
979 .rst_i (rst_i),
980 // From pipeline
981 .stall_a (stall_a),
982 .stall_x (stall_x),
983 .stall_m (stall_m),
984 .kill_x (kill_x),
985 .kill_m (kill_m),
986 .exception_m (exception_m),
987 .store_operand_x (store_operand_x),
988 .load_store_address_x (adder_result_x),
989 .load_store_address_m (operand_m),
990 .load_store_address_w (operand_w[1:0]),
991 .load_x (load_x),
992 .store_x (store_x),
993 .load_q_x (load_q_x),
994 .store_q_x (store_q_x),
995 .load_q_m (load_q_m),
996 .store_q_m (store_q_m),
997 .sign_extend_x (sign_extend_x),
998 .size_x (size_x),
999 `ifdef CFG_DCACHE_ENABLED
1000 .dflush (dflush_m),
1001 `endif
1002 `ifdef CFG_IROM_ENABLED
1003 .irom_data_m (irom_data_m),
1004 `endif
1005 // From Wishbone
1006 .d_dat_i (D_DAT_I),
1007 .d_ack_i (D_ACK_I),
1008 .d_err_i (D_ERR_I),
1009 .d_rty_i (D_RTY_I),
1010 // ----- Outputs -------
1011 // To pipeline
1012 `ifdef CFG_DCACHE_ENABLED
1013 .dcache_refill_request (dcache_refill_request),
1014 .dcache_restart_request (dcache_restart_request),
1015 .dcache_stall_request (dcache_stall_request),
1016 .dcache_refilling (dcache_refilling),
1017 `endif
1018 `ifdef CFG_IROM_ENABLED
1019 .irom_store_data_m (irom_store_data_m),
1020 .irom_address_xm (irom_address_xm),
1021 .irom_we_xm (irom_we_xm),
1022 .irom_stall_request_x (irom_stall_request_x),
1023 `endif
1024 .load_data_w (load_data_w),
1025 .stall_wb_load (stall_wb_load),
1026 // To Wishbone
1027 .d_dat_o (D_DAT_O),
1028 .d_adr_o (D_ADR_O),
1029 .d_cyc_o (D_CYC_O),
1030 .d_sel_o (D_SEL_O),
1031 .d_stb_o (D_STB_O),
1032 .d_we_o (D_WE_O),
1033 .d_cti_o (D_CTI_O),
1034 .d_lock_o (D_LOCK_O),
1035 .d_bte_o (D_BTE_O)
1036 );
1037
1038 // Adder
1039 lm32_adder adder (
1040 // ----- Inputs -------
1041 .adder_op_x (adder_op_x),
1042 .adder_op_x_n (adder_op_x_n),
1043 .operand_0_x (operand_0_x),
1044 .operand_1_x (operand_1_x),
1045 // ----- Outputs -------
1046 .adder_result_x (adder_result_x),
1047 .adder_carry_n_x (adder_carry_n_x),
1048 .adder_overflow_x (adder_overflow_x)
1049 );
1050
1051 // Logic operations
1052 lm32_logic_op logic_op (
1053 // ----- Inputs -------
1054 .logic_op_x (logic_op_x),
1055 .operand_0_x (operand_0_x),
1056
1057 .operand_1_x (operand_1_x),
1058 // ----- Outputs -------
1059 .logic_result_x (logic_result_x)
1060 );
1061
1062 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
1063 // Pipelined barrel-shifter
1064 lm32_shifter shifter (
1065 // ----- Inputs -------
1066 .clk_i (clk_i),
1067 .rst_i (rst_i),
1068 .stall_x (stall_x),
1069 .direction_x (direction_x),
1070 .sign_extend_x (sign_extend_x),
1071 .operand_0_x (operand_0_x),
1072 .operand_1_x (operand_1_x),
1073 // ----- Outputs -------
1074 .shifter_result_m (shifter_result_m)
1075 );
1076 `endif
1077
1078 `ifdef CFG_PL_MULTIPLY_ENABLED
1079 // Pipeline fixed-point multiplier
1080 lm32_multiplier multiplier (
1081 // ----- Inputs -------
1082 .clk_i (clk_i),
1083 .rst_i (rst_i),
1084 .stall_x (stall_x),
1085 .stall_m (stall_m),
1086 .operand_0 (d_result_0),
1087 .operand_1 (d_result_1),
1088 // ----- Outputs -------
1089 .result (multiplier_result_w)
1090 );
1091 `endif
1092
1093 `ifdef LM32_MC_ARITHMETIC_ENABLED
1094 // Multi-cycle arithmetic
1095 lm32_mc_arithmetic mc_arithmetic (
1096 // ----- Inputs -------
1097 .clk_i (clk_i),
1098 .rst_i (rst_i),
1099 .stall_d (stall_d),
1100 .kill_x (kill_x),
1101 `ifdef CFG_MC_DIVIDE_ENABLED
1102 .divide_d (divide_q_d),
1103 .modulus_d (modulus_q_d),
1104 `endif
1105 `ifdef CFG_MC_MULTIPLY_ENABLED
1106 .multiply_d (multiply_q_d),
1107 `endif
1108 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
1109 .shift_left_d (shift_left_q_d),
1110 .shift_right_d (shift_right_q_d),
1111 .sign_extend_d (sign_extend_d),
1112 `endif
1113 .operand_0_d (d_result_0),
1114 .operand_1_d (d_result_1),
1115 // ----- Outputs -------
1116 .result_x (mc_result_x),
1117 `ifdef CFG_MC_DIVIDE_ENABLED
1118 .divide_by_zero_x (divide_by_zero_x),
1119 `endif
1120 .stall_request_x (mc_stall_request_x)
1121 );
1122 `endif
1123
1124 `ifdef CFG_INTERRUPTS_ENABLED
1125 // Interrupt unit
1126 lm32_interrupt interrupt_unit (
1127 // ----- Inputs -------
1128 .clk_i (clk_i),
1129 .rst_i (rst_i),
1130 // From external devices
1131 .interrupt (interrupt),
1132 // From pipeline
1133 .stall_x (stall_x),
1134 `ifdef CFG_DEBUG_ENABLED
1135 .non_debug_exception (non_debug_exception_q_w),
1136 .debug_exception (debug_exception_q_w),
1137 `else
1138 .exception (exception_q_w),
1139 `endif
1140 .eret_q_x (eret_q_x),
1141 `ifdef CFG_DEBUG_ENABLED
1142 .bret_q_x (bret_q_x),
1143 `endif
1144 .csr (csr_x),
1145 .csr_write_data (operand_1_x),
1146 .csr_write_enable (csr_write_enable_q_x),
1147 // ----- Outputs -------
1148 .interrupt_exception (interrupt_exception),
1149 // To pipeline
1150 .csr_read_data (interrupt_csr_read_data_x)
1151 );
1152 `endif
1153
1154 `ifdef CFG_JTAG_ENABLED
1155 // JTAG interface
1156 lm32_jtag jtag (
1157 // ----- Inputs -------
1158 .clk_i (clk_i),
1159 .rst_i (rst_i),
1160 // From JTAG
1161 .jtag_clk (jtag_clk),
1162 .jtag_update (jtag_update),
1163 .jtag_reg_q (jtag_reg_q),
1164 .jtag_reg_addr_q (jtag_reg_addr_q),
1165 // From pipeline
1166 `ifdef CFG_JTAG_UART_ENABLED
1167 .csr (csr_x),
1168 .csr_write_data (operand_1_x),
1169 .csr_write_enable (csr_write_enable_q_x),
1170 .stall_x (stall_x),
1171 `endif
1172 `ifdef CFG_HW_DEBUG_ENABLED
1173 .jtag_read_data (jtag_read_data),
1174 .jtag_access_complete (jtag_access_complete),
1175 `endif
1176 `ifdef CFG_DEBUG_ENABLED
1177 .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
1178 `endif
1179 // ----- Outputs -------
1180 // To pipeline
1181 `ifdef CFG_JTAG_UART_ENABLED
1182 .jtx_csr_read_data (jtx_csr_read_data),
1183 .jrx_csr_read_data (jrx_csr_read_data),
1184 `endif
1185 `ifdef CFG_HW_DEBUG_ENABLED
1186 .jtag_csr_write_enable (jtag_csr_write_enable),
1187 .jtag_csr_write_data (jtag_csr_write_data),
1188 .jtag_csr (jtag_csr),
1189 .jtag_read_enable (jtag_read_enable),
1190 .jtag_write_enable (jtag_write_enable),
1191 .jtag_write_data (jtag_write_data),
1192 .jtag_address (jtag_address),
1193 `endif
1194 `ifdef CFG_DEBUG_ENABLED
1195 .jtag_break (jtag_break),
1196 .jtag_reset (reset_exception),
1197 `endif
1198 // To JTAG
1199 .jtag_reg_d (jtag_reg_d),
1200 .jtag_reg_addr_d (jtag_reg_addr_d)
1201 );
1202 `endif
1203
1204 `ifdef CFG_DEBUG_ENABLED
1205 // Debug unit
1206 lm32_debug #(
1207 .breakpoints (breakpoints),
1208 .watchpoints (watchpoints)
1209 ) hw_debug (
1210 // ----- Inputs -------
1211 .clk_i (clk_i),
1212 .rst_i (rst_i),
1213 .pc_x (pc_x),
1214 .load_x (load_x),
1215 .store_x (store_x),
1216 .load_store_address_x (adder_result_x),
1217 .csr_write_enable_x (csr_write_enable_q_x),
1218 .csr_write_data (operand_1_x),
1219 .csr_x (csr_x),
1220 `ifdef CFG_HW_DEBUG_ENABLED
1221 .jtag_csr_write_enable (jtag_csr_write_enable),
1222 .jtag_csr_write_data (jtag_csr_write_data),
1223 .jtag_csr (jtag_csr),
1224 `endif
1225 `ifdef LM32_SINGLE_STEP_ENABLED
1226 .eret_q_x (eret_q_x),
1227 .bret_q_x (bret_q_x),
1228 .stall_x (stall_x),
1229 .exception_x (exception_x),
1230 .q_x (q_x),
1231 `ifdef CFG_DCACHE_ENABLED
1232 .dcache_refill_request (dcache_refill_request),
1233 `endif
1234 `endif
1235 // ----- Outputs -------
1236 `ifdef LM32_SINGLE_STEP_ENABLED
1237 .dc_ss (dc_ss),
1238 `endif
1239 .dc_re (dc_re),
1240 .bp_match (bp_match),
1241 .wp_match (wp_match)
1242 );
1243 `endif
1244
1245 // Register file
1246
1247 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
1248 /*----------------------------------------------------------------------
1249 Register File is implemented using EBRs. There can be three accesses to
1250 the register file in each cycle: two reads and one write. On-chip block
1251 RAM has two read/write ports. To accomodate three accesses, two on-chip
1252 block RAMs are used (each register file "write" is made to both block
1253 RAMs).
1254
1255 One limitation of the on-chip block RAMs is that one cannot perform a
1256 read and write to same location in a cycle (if this is done, then the
1257 data read out is indeterminate).
1258 ----------------------------------------------------------------------*/
1259 wire [31:0] regfile_data_0, regfile_data_1;
1260 reg [31:0] w_result_d;
1261 reg regfile_raw_0, regfile_raw_0_nxt;
1262 reg regfile_raw_1, regfile_raw_1_nxt;
1263
1264 /*----------------------------------------------------------------------
1265 Check if read and write is being performed to same register in current
1266 cycle? This is done by comparing the read and write IDXs.
1267 ----------------------------------------------------------------------*/
1268 always @(reg_write_enable_q_w or write_idx_w or instruction_f)
1269 begin
1270 if (reg_write_enable_q_w
1271 && (write_idx_w == instruction_f[25:21]))
1272 regfile_raw_0_nxt = 1'b1;
1273 else
1274 regfile_raw_0_nxt = 1'b0;
1275
1276 if (reg_write_enable_q_w
1277 && (write_idx_w == instruction_f[20:16]))
1278 regfile_raw_1_nxt = 1'b1;
1279 else
1280 regfile_raw_1_nxt = 1'b0;
1281 end
1282
1283 /*----------------------------------------------------------------------
1284 Select latched (delayed) write value or data from register file. If
1285 read in previous cycle was performed to register written to in same
1286 cycle, then latched (delayed) write value is selected.
1287 ----------------------------------------------------------------------*/
1288 always @(regfile_raw_0 or w_result_d or regfile_data_0)
1289 if (regfile_raw_0)
1290 reg_data_live_0 = w_result_d;
1291 else
1292 reg_data_live_0 = regfile_data_0;
1293
1294 /*----------------------------------------------------------------------
1295 Select latched (delayed) write value or data from register file. If
1296 read in previous cycle was performed to register written to in same
1297 cycle, then latched (delayed) write value is selected.
1298 ----------------------------------------------------------------------*/
1299 always @(regfile_raw_1 or w_result_d or regfile_data_1)
1300 if (regfile_raw_1)
1301 reg_data_live_1 = w_result_d;
1302 else
1303 reg_data_live_1 = regfile_data_1;
1304
1305 /*----------------------------------------------------------------------
1306 Latch value written to register file
1307 ----------------------------------------------------------------------*/
1308 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1309 if (rst_i == `TRUE)
1310 begin
1311 regfile_raw_0 <= 1'b0;
1312 regfile_raw_1 <= 1'b0;
1313 w_result_d <= 32'b0;
1314 end
1315 else
1316 begin
1317 regfile_raw_0 <= regfile_raw_0_nxt;
1318 regfile_raw_1 <= regfile_raw_1_nxt;
1319 w_result_d <= w_result;
1320 end
1321
1322 /*----------------------------------------------------------------------
1323 Register file instantiation as Pseudo-Dual Port EBRs.
1324 ----------------------------------------------------------------------*/
1325 // Modified by GSI: removed non-portable RAM instantiation
1326 lm32_dp_ram
1327 #(
1328 // ----- Parameters -----
1329 .addr_depth(1<<5),
1330 .addr_width(5),
1331 .data_width(32)
1332 )
1333 reg_0
1334 (
1335 // ----- Inputs -----
1336 .clk_i (clk_i),
1337 .rst_i (rst_i),
1338 .we_i (reg_write_enable_q_w),
1339 .wdata_i (w_result),
1340 .waddr_i (write_idx_w),
1341 .raddr_i (instruction_f[25:21]),
1342 // ----- Outputs -----
1343 .rdata_o (regfile_data_0)
1344 );
1345
1346 lm32_dp_ram
1347 #(
1348 .addr_depth(1<<5),
1349 .addr_width(5),
1350 .data_width(32)
1351 )
1352 reg_1
1353 (
1354 // ----- Inputs -----
1355 .clk_i (clk_i),
1356 .rst_i (rst_i),
1357 .we_i (reg_write_enable_q_w),
1358 .wdata_i (w_result),
1359 .waddr_i (write_idx_w),
1360 .raddr_i (instruction_f[20:16]),
1361 // ----- Outputs -----
1362 .rdata_o (regfile_data_1)
1363 );
1364 `endif
1365
1366 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
1367 pmi_ram_dp
1368 #(
1369 // ----- Parameters -----
1370 .pmi_wr_addr_depth(1<<5),
1371 .pmi_wr_addr_width(5),
1372 .pmi_wr_data_width(32),
1373 .pmi_rd_addr_depth(1<<5),
1374 .pmi_rd_addr_width(5),
1375 .pmi_rd_data_width(32),
1376 .pmi_regmode("noreg"),
1377 .pmi_gsr("enable"),
1378 .pmi_resetmode("sync"),
1379 .pmi_init_file("none"),
1380 .pmi_init_file_format("binary"),
1381 .pmi_family(`LATTICE_FAMILY),
1382 .module_type("pmi_ram_dp")
1383 )
1384 reg_0
1385 (
1386 // ----- Inputs -----
1387 .Data(w_result),
1388 .WrAddress(write_idx_w),
1389 .RdAddress(read_idx_0_d),
1390 .WrClock(clk_i),
1391 .RdClock(clk_n_i),
1392 .WrClockEn(`TRUE),
1393 .RdClockEn(stall_f == `FALSE),
1394 .WE(reg_write_enable_q_w),
1395 .Reset(rst_i),
1396 // ----- Outputs -----
1397 .Q(reg_data_0)
1398 );
1399
1400 pmi_ram_dp
1401 #(
1402 // ----- Parameters -----
1403 .pmi_wr_addr_depth(1<<5),
1404 .pmi_wr_addr_width(5),
1405 .pmi_wr_data_width(32),
1406 .pmi_rd_addr_depth(1<<5),
1407 .pmi_rd_addr_width(5),
1408 .pmi_rd_data_width(32),
1409 .pmi_regmode("noreg"),
1410 .pmi_gsr("enable"),
1411 .pmi_resetmode("sync"),
1412 .pmi_init_file("none"),
1413 .pmi_init_file_format("binary"),
1414 .pmi_family(`LATTICE_FAMILY),
1415 .module_type("pmi_ram_dp")
1416 )
1417 reg_1
1418 (
1419 // ----- Inputs -----
1420 .Data(w_result),
1421 .WrAddress(write_idx_w),
1422 .RdAddress(read_idx_1_d),
1423 .WrClock(clk_i),
1424 .RdClock(clk_n_i),
1425 .WrClockEn(`TRUE),
1426 .RdClockEn(stall_f == `FALSE),
1427 .WE(reg_write_enable_q_w),
1428 .Reset(rst_i),
1429 // ----- Outputs -----
1430 .Q(reg_data_1)
1431 );
1432 `endif
1433
1434
1435 /////////////////////////////////////////////////////
1436 // Combinational Logic
1437 /////////////////////////////////////////////////////
1438
1439 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
1440 // Select between buffered and live data from register file
1441 assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
1442 assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
1443 `endif
1444 `ifdef LM32_EBR_REGISTER_FILE
1445 `else
1446 // Register file read ports
1447 assign reg_data_0 = registers[read_idx_0_d];
1448 assign reg_data_1 = registers[read_idx_1_d];
1449 `endif
1450
1451 // Detect read-after-write hazzards
1452 assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
1453 assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
1454 assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
1455 assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
1456 assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
1457 assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
1458
1459 // Interlock detection - Raise an interlock for RAW hazzards
1460 always @(*)
1461 begin
1462 if ( ( (x_bypass_enable_x == `FALSE)
1463 && ( ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
1464 || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
1465 )
1466 )
1467 || ( (m_bypass_enable_m == `FALSE)
1468 && ( ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
1469 || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
1470 )
1471 )
1472 )
1473 interlock = `TRUE;
1474 else
1475 interlock = `FALSE;
1476 end
1477
1478 // Bypass for reg port 0
1479 always @(*)
1480 begin
1481 if (raw_x_0 == `TRUE)
1482 bypass_data_0 = x_result;
1483 else if (raw_m_0 == `TRUE)
1484 bypass_data_0 = m_result;
1485 else if (raw_w_0 == `TRUE)
1486 bypass_data_0 = w_result;
1487 else
1488 bypass_data_0 = reg_data_0;
1489 end
1490
1491 // Bypass for reg port 1
1492 always @(*)
1493 begin
1494 if (raw_x_1 == `TRUE)
1495 bypass_data_1 = x_result;
1496 else if (raw_m_1 == `TRUE)
1497 bypass_data_1 = m_result;
1498 else if (raw_w_1 == `TRUE)
1499 bypass_data_1 = w_result;
1500 else
1501 bypass_data_1 = reg_data_1;
1502 end
1503
1504 /*----------------------------------------------------------------------
1505 Branch prediction is performed in D stage of pipeline. Only PC-relative
1506 branches are predicted: forward-pointing conditional branches are not-
1507 taken, while backward-pointing conditional branches are taken.
1508 Unconditional branches are always predicted taken!
1509 ----------------------------------------------------------------------*/
1510 assign branch_predict_d = bi_unconditional | bi_conditional;
1511 assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
1512
1513 // Compute branch target address: Branch PC PLUS Offset
1514 assign branch_target_d = pc_d + branch_offset_d;
1515
1516 // Compute fetch address. Address of instruction sequentially after the
1517 // branch if branch is not taken. Target address of branch is branch is
1518 // taken
1519 assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
1520
1521 // D stage result selection
1522 always @(*)
1523 begin
1524 d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
1525 case (d_result_sel_1_d)
1526 `LM32_D_RESULT_SEL_1_ZERO: d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
1527 `LM32_D_RESULT_SEL_1_REG_1: d_result_1 = bypass_data_1;
1528 `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
1529 default: d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
1530 endcase
1531 end
1532
1533 `ifdef CFG_USER_ENABLED
1534 // Operands for user-defined instructions
1535 assign user_operand_0 = operand_0_x;
1536 assign user_operand_1 = operand_1_x;
1537 `endif
1538
1539 `ifdef CFG_SIGN_EXTEND_ENABLED
1540 // Sign-extension
1541 assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
1542 assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
1543 assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
1544 `endif
1545
1546 `ifdef LM32_NO_BARREL_SHIFT
1547 // Only single bit shift operations are supported when barrel-shifter isn't implemented
1548 assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
1549 `endif
1550
1551 // Condition evaluation
1552 assign cmp_zero = operand_0_x == operand_1_x;
1553 assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
1554 assign cmp_overflow = adder_overflow_x;
1555 assign cmp_carry_n = adder_carry_n_x;
1556 always @(*)
1557 begin
1558 case (condition_x)
1559 `LM32_CONDITION_U1: condition_met_x = `TRUE;
1560 `LM32_CONDITION_U2: condition_met_x = `TRUE;
1561 `LM32_CONDITION_E: condition_met_x = cmp_zero;
1562 `LM32_CONDITION_NE: condition_met_x = !cmp_zero;
1563 `LM32_CONDITION_G: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
1564 `LM32_CONDITION_GU: condition_met_x = cmp_carry_n && !cmp_zero;
1565 `LM32_CONDITION_GE: condition_met_x = cmp_negative == cmp_overflow;
1566 `LM32_CONDITION_GEU: condition_met_x = cmp_carry_n;
1567 default: condition_met_x = 1'bx;
1568 endcase
1569 end
1570
1571 // X stage result selection
1572 always @(*)
1573 begin
1574 x_result = x_result_sel_add_x ? adder_result_x
1575 : x_result_sel_csr_x ? csr_read_data_x
1576 `ifdef CFG_SIGN_EXTEND_ENABLED
1577 : x_result_sel_sext_x ? sext_result_x
1578 `endif
1579 `ifdef CFG_USER_ENABLED
1580 : x_result_sel_user_x ? user_result
1581 `endif
1582 `ifdef LM32_NO_BARREL_SHIFT
1583 : x_result_sel_shift_x ? shifter_result_x
1584 `endif
1585 `ifdef LM32_MC_ARITHMETIC_ENABLED
1586 : x_result_sel_mc_arith_x ? mc_result_x
1587 `endif
1588 : logic_result_x;
1589 end
1590
1591 // M stage result selection
1592 always @(*)
1593 begin
1594 m_result = m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
1595 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
1596 : m_result_sel_shift_m ? shifter_result_m
1597 `endif
1598 : operand_m;
1599 end
1600
1601 // W stage result selection
1602 always @(*)
1603 begin
1604 w_result = w_result_sel_load_w ? load_data_w
1605 `ifdef CFG_PL_MULTIPLY_ENABLED
1606 : w_result_sel_mul_w ? multiplier_result_w
1607 `endif
1608 : operand_w;
1609 end
1610
1611 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1612 // Indicate when a branch should be taken in X stage
1613 assign branch_taken_x = (stall_x == `FALSE)
1614 && ( (branch_x == `TRUE)
1615 && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2))
1616 && (valid_x == `TRUE)
1617 && (branch_predict_x == `FALSE)
1618 );
1619 `endif
1620
1621 // Indicate when a branch should be taken in M stage (exceptions are a type of branch)
1622 assign branch_taken_m = (stall_m == `FALSE)
1623 && ( ( (branch_m == `TRUE)
1624 && (valid_m == `TRUE)
1625 && ( ( (condition_met_m == `TRUE)
1626 && (branch_predict_taken_m == `FALSE)
1627 )
1628 || ( (condition_met_m == `FALSE)
1629 && (branch_predict_m == `TRUE)
1630 && (branch_predict_taken_m == `TRUE)
1631 )
1632 )
1633 )
1634 || (exception_m == `TRUE)
1635 );
1636
1637 // Indicate when a branch in M stage is mispredicted as being taken
1638 assign branch_mispredict_taken_m = (condition_met_m == `FALSE)
1639 && (branch_predict_m == `TRUE)
1640 && (branch_predict_taken_m == `TRUE);
1641
1642 // Indicate when a branch in M stage will cause flush in X stage
1643 assign branch_flushX_m = (stall_m == `FALSE)
1644 && ( ( (branch_m == `TRUE)
1645 && (valid_m == `TRUE)
1646 && ( (condition_met_m == `TRUE)
1647 || ( (condition_met_m == `FALSE)
1648 && (branch_predict_m == `TRUE)
1649 && (branch_predict_taken_m == `TRUE)
1650 )
1651 )
1652 )
1653 || (exception_m == `TRUE)
1654 );
1655
1656 // Generate signal that will kill instructions in each pipeline stage when necessary
1657 assign kill_f = ( (valid_d == `TRUE)
1658 && (branch_predict_taken_d == `TRUE)
1659 )
1660 || (branch_taken_m == `TRUE)
1661 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1662 || (branch_taken_x == `TRUE)
1663 `endif
1664 `ifdef CFG_ICACHE_ENABLED
1665 || (icache_refill_request == `TRUE)
1666 `endif
1667 `ifdef CFG_DCACHE_ENABLED
1668 || (dcache_refill_request == `TRUE)
1669 `endif
1670 ;
1671 assign kill_d = (branch_taken_m == `TRUE)
1672 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1673 || (branch_taken_x == `TRUE)
1674 `endif
1675 `ifdef CFG_ICACHE_ENABLED
1676 || (icache_refill_request == `TRUE)
1677 `endif
1678 `ifdef CFG_DCACHE_ENABLED
1679 || (dcache_refill_request == `TRUE)
1680 `endif
1681 ;
1682 assign kill_x = (branch_flushX_m == `TRUE)
1683 `ifdef CFG_DCACHE_ENABLED
1684 || (dcache_refill_request == `TRUE)
1685 `endif
1686 ;
1687 assign kill_m = `FALSE
1688 `ifdef CFG_DCACHE_ENABLED
1689 || (dcache_refill_request == `TRUE)
1690 `endif
1691 ;
1692 assign kill_w = `FALSE
1693 `ifdef CFG_DCACHE_ENABLED
1694 || (dcache_refill_request == `TRUE)
1695 `endif
1696 ;
1697
1698 // Exceptions
1699
1700 `ifdef CFG_DEBUG_ENABLED
1701 assign breakpoint_exception = ( ( (break_x == `TRUE)
1702 || (bp_match == `TRUE)
1703 )
1704 && (valid_x == `TRUE)
1705 )
1706 `ifdef CFG_JTAG_ENABLED
1707 || (jtag_break == `TRUE)
1708 `endif
1709 `ifdef CFG_EXTERNAL_BREAK_ENABLED
1710 || (ext_break_r == `TRUE)
1711 `endif
1712 ;
1713 `endif
1714
1715 `ifdef CFG_DEBUG_ENABLED
1716 assign watchpoint_exception = wp_match == `TRUE;
1717 `endif
1718
1719 `ifdef CFG_BUS_ERRORS_ENABLED
1720 assign instruction_bus_error_exception = ( (bus_error_x == `TRUE)
1721 && (valid_x == `TRUE)
1722 );
1723 assign data_bus_error_exception = data_bus_error_seen == `TRUE;
1724 `endif
1725
1726 `ifdef CFG_MC_DIVIDE_ENABLED
1727 assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
1728 `endif
1729
1730 assign system_call_exception = ( (scall_x == `TRUE)
1731 `ifdef CFG_BUS_ERRORS_ENABLED
1732 && (valid_x == `TRUE)
1733 `endif
1734 );
1735
1736 `ifdef CFG_DEBUG_ENABLED
1737 assign debug_exception_x = (breakpoint_exception == `TRUE)
1738 || (watchpoint_exception == `TRUE)
1739 ;
1740
1741 assign non_debug_exception_x = (system_call_exception == `TRUE)
1742 `ifdef CFG_JTAG_ENABLED
1743 || (reset_exception == `TRUE)
1744 `endif
1745 `ifdef CFG_BUS_ERRORS_ENABLED
1746 || (instruction_bus_error_exception == `TRUE)
1747 || (data_bus_error_exception == `TRUE)
1748 `endif
1749 `ifdef CFG_MC_DIVIDE_ENABLED
1750 || (divide_by_zero_exception == `TRUE)
1751 `endif
1752 `ifdef CFG_INTERRUPTS_ENABLED
1753 || ( (interrupt_exception == `TRUE)
1754 `ifdef LM32_SINGLE_STEP_ENABLED
1755 && (dc_ss == `FALSE)
1756 `endif
1757 `ifdef CFG_BUS_ERRORS_ENABLED
1758 && (store_q_m == `FALSE)
1759 && (D_CYC_O == `FALSE)
1760 `endif
1761 )
1762 `endif
1763 ;
1764
1765 assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
1766 `else
1767 assign exception_x = (system_call_exception == `TRUE)
1768 `ifdef CFG_BUS_ERRORS_ENABLED
1769 || (instruction_bus_error_exception == `TRUE)
1770 || (data_bus_error_exception == `TRUE)
1771 `endif
1772 `ifdef CFG_MC_DIVIDE_ENABLED
1773 || (divide_by_zero_exception == `TRUE)
1774 `endif
1775 `ifdef CFG_INTERRUPTS_ENABLED
1776 || ( (interrupt_exception == `TRUE)
1777 `ifdef LM32_SINGLE_STEP_ENABLED
1778 && (dc_ss == `FALSE)
1779 `endif
1780 `ifdef CFG_BUS_ERRORS_ENABLED
1781 && (store_q_m == `FALSE)
1782 && (D_CYC_O == `FALSE)
1783 `endif
1784 )
1785 `endif
1786 ;
1787 `endif
1788
1789 // Exception ID
1790 always @(*)
1791 begin
1792 `ifdef CFG_DEBUG_ENABLED
1793 `ifdef CFG_JTAG_ENABLED
1794 if (reset_exception == `TRUE)
1795 eid_x = `LM32_EID_RESET;
1796 else
1797 `endif
1798 `ifdef CFG_BUS_ERRORS_ENABLED
1799 if (data_bus_error_exception == `TRUE)
1800 eid_x = `LM32_EID_DATA_BUS_ERROR;
1801 else
1802 `endif
1803 if (breakpoint_exception == `TRUE)
1804 eid_x = `LM32_EID_BREAKPOINT;
1805 else
1806 `endif
1807 `ifdef CFG_BUS_ERRORS_ENABLED
1808 if (data_bus_error_exception == `TRUE)
1809 eid_x = `LM32_EID_DATA_BUS_ERROR;
1810 else
1811 if (instruction_bus_error_exception == `TRUE)
1812 eid_x = `LM32_EID_INST_BUS_ERROR;
1813 else
1814 `endif
1815 `ifdef CFG_DEBUG_ENABLED
1816 if (watchpoint_exception == `TRUE)
1817 eid_x = `LM32_EID_WATCHPOINT;
1818 else
1819 `endif
1820 `ifdef CFG_MC_DIVIDE_ENABLED
1821 if (divide_by_zero_exception == `TRUE)
1822 eid_x = `LM32_EID_DIVIDE_BY_ZERO;
1823 else
1824 `endif
1825 `ifdef CFG_INTERRUPTS_ENABLED
1826 if ( (interrupt_exception == `TRUE)
1827 `ifdef LM32_SINGLE_STEP_ENABLED
1828 && (dc_ss == `FALSE)
1829 `endif
1830 )
1831 eid_x = `LM32_EID_INTERRUPT;
1832 else
1833 `endif
1834 eid_x = `LM32_EID_SCALL;
1835 end
1836
1837 // Stall generation
1838
1839 assign stall_a = (stall_f == `TRUE);
1840
1841 assign stall_f = (stall_d == `TRUE);
1842
1843 assign stall_d = (stall_x == `TRUE)
1844 || ( (interlock == `TRUE)
1845 && (kill_d == `FALSE)
1846 )
1847 || ( ( (eret_d == `TRUE)
1848 || (scall_d == `TRUE)
1849 `ifdef CFG_BUS_ERRORS_ENABLED
1850 || (bus_error_d == `TRUE)
1851 `endif
1852 )
1853 && ( (load_q_x == `TRUE)
1854 || (load_q_m == `TRUE)
1855 || (store_q_x == `TRUE)
1856 || (store_q_m == `TRUE)
1857 || (D_CYC_O == `TRUE)
1858 )
1859 && (kill_d == `FALSE)
1860 )
1861 `ifdef CFG_DEBUG_ENABLED
1862 || ( ( (break_d == `TRUE)
1863 || (bret_d == `TRUE)
1864 )
1865 && ( (load_q_x == `TRUE)
1866 || (store_q_x == `TRUE)
1867 || (load_q_m == `TRUE)
1868 || (store_q_m == `TRUE)
1869 || (D_CYC_O == `TRUE)
1870 )
1871 && (kill_d == `FALSE)
1872 )
1873 `endif
1874 || ( (csr_write_enable_d == `TRUE)
1875 && (load_q_x == `TRUE)
1876 )
1877 ;
1878
1879 assign stall_x = (stall_m == `TRUE)
1880 `ifdef LM32_MC_ARITHMETIC_ENABLED
1881 || ( (mc_stall_request_x == `TRUE)
1882 && (kill_x == `FALSE)
1883 )
1884 `endif
1885 `ifdef CFG_IROM_ENABLED
1886 // Stall load/store instruction in D stage if there is an ongoing store
1887 // operation to instruction ROM in M stage
1888 || ( (irom_stall_request_x == `TRUE)
1889 && ( (load_d == `TRUE)
1890 || (store_d == `TRUE)
1891 )
1892 )
1893 `endif
1894 ;
1895
1896 assign stall_m = (stall_wb_load == `TRUE)
1897 `ifdef CFG_SIZE_OVER_SPEED
1898 || (D_CYC_O == `TRUE)
1899 `else
1900 || ( (D_CYC_O == `TRUE)
1901 && ( (store_m == `TRUE)
1902 /*
1903 Bug: Following loop does not allow interrupts to be services since
1904 either D_CYC_O or store_m is always high during entire duration of
1905 loop.
1906 L1: addi r1, r1, 1
1907 sw (r2,0), r1
1908 bi L1
1909
1910 Introduce a single-cycle stall when a wishbone cycle is in progress
1911 and a new store instruction is in Execute stage and a interrupt
1912 exception has occured. This stall will ensure that D_CYC_O and
1913 store_m will both be low for one cycle.
1914 */
1915 `ifdef CFG_INTERRUPTS_ENABLED
1916 || ((store_x == `TRUE) && (interrupt_exception == `TRUE))
1917 `endif
1918 || (load_m == `TRUE)
1919 || (load_x == `TRUE)
1920 )
1921 )
1922 `endif
1923 `ifdef CFG_DCACHE_ENABLED
1924 || (dcache_stall_request == `TRUE) // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
1925 `endif
1926 `ifdef CFG_ICACHE_ENABLED
1927 || (icache_stall_request == `TRUE) // Pipeline needs to be stalled otherwise branches may be lost
1928 || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE)))
1929 `else
1930 `ifdef CFG_IWB_ENABLED
1931 || (I_CYC_O == `TRUE)
1932 `endif
1933 `endif
1934 `ifdef CFG_USER_ENABLED
1935 || ( (user_valid == `TRUE) // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
1936 && (user_complete == `FALSE)
1937 )
1938 `endif
1939 ;
1940
1941 // Qualify state changing control signals
1942 `ifdef LM32_MC_ARITHMETIC_ENABLED
1943 assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
1944 `endif
1945 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
1946 assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
1947 assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
1948 `endif
1949 `ifdef CFG_MC_MULTIPLY_ENABLED
1950 assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
1951 `endif
1952 `ifdef CFG_MC_DIVIDE_ENABLED
1953 assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
1954 assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
1955 `endif
1956 assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
1957 assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
1958 assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
1959 `ifdef CFG_DEBUG_ENABLED
1960 assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
1961 `endif
1962 assign load_q_x = (load_x == `TRUE)
1963 && (q_x == `TRUE)
1964 `ifdef CFG_DEBUG_ENABLED
1965 && (bp_match == `FALSE)
1966 `endif
1967 ;
1968 assign store_q_x = (store_x == `TRUE)
1969 && (q_x == `TRUE)
1970 `ifdef CFG_DEBUG_ENABLED
1971 && (bp_match == `FALSE)
1972 `endif
1973 ;
1974 `ifdef CFG_USER_ENABLED
1975 assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
1976 `endif
1977 assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
1978 assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
1979 assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
1980 `ifdef CFG_DEBUG_ENABLED
1981 assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
1982 assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));
1983 `else
1984 assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));
1985 `endif
1986 // Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
1987 assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE);
1988 assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
1989 assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
1990 // The enable that actually does write the registers needs to be qualified with kill
1991 assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
1992
1993 // Configuration (CFG) CSR
1994 assign cfg = {
1995 `LM32_REVISION,
1996 watchpoints[3:0],
1997 breakpoints[3:0],
1998 interrupts[5:0],
1999 `ifdef CFG_JTAG_UART_ENABLED
2000 `TRUE,
2001 `else
2002 `FALSE,
2003 `endif
2004 `ifdef CFG_ROM_DEBUG_ENABLED
2005 `TRUE,
2006 `else
2007 `FALSE,
2008 `endif
2009 `ifdef CFG_HW_DEBUG_ENABLED
2010 `TRUE,
2011 `else
2012 `FALSE,
2013 `endif
2014 `ifdef CFG_DEBUG_ENABLED
2015 `TRUE,
2016 `else
2017 `FALSE,
2018 `endif
2019 `ifdef CFG_ICACHE_ENABLED
2020 `TRUE,
2021 `else
2022 `FALSE,
2023 `endif
2024 `ifdef CFG_DCACHE_ENABLED
2025 `TRUE,
2026 `else
2027 `FALSE,
2028 `endif
2029 `ifdef CFG_CYCLE_COUNTER_ENABLED
2030 `TRUE,
2031 `else
2032 `FALSE,
2033 `endif
2034 `ifdef CFG_USER_ENABLED
2035 `TRUE,
2036 `else
2037 `FALSE,
2038 `endif
2039 `ifdef CFG_SIGN_EXTEND_ENABLED
2040 `TRUE,
2041 `else
2042 `FALSE,
2043 `endif
2044 `ifdef LM32_BARREL_SHIFT_ENABLED
2045 `TRUE,
2046 `else
2047 `FALSE,
2048 `endif
2049 `ifdef CFG_MC_DIVIDE_ENABLED
2050 `TRUE,
2051 `else
2052 `FALSE,
2053 `endif
2054 `ifdef LM32_MULTIPLY_ENABLED
2055 `TRUE
2056 `else
2057 `FALSE
2058 `endif
2059 };
2060
2061 assign cfg2 = {
2062 30'b0,
2063 `ifdef CFG_IROM_ENABLED
2064 `TRUE,
2065 `else
2066 `FALSE,
2067 `endif
2068 `ifdef CFG_DRAM_ENABLED
2069 `TRUE
2070 `else
2071 `FALSE
2072 `endif
2073 };
2074
2075 // Cache flush
2076 `ifdef CFG_ICACHE_ENABLED
2077 assign iflush = ( (csr_write_enable_d == `TRUE)
2078 && (csr_d == `LM32_CSR_ICC)
2079 && (stall_d == `FALSE)
2080 && (kill_d == `FALSE)
2081 && (valid_d == `TRUE))
2082 // Added by GSI: needed to flush cache after loading firmware per JTAG
2083 `ifdef CFG_HW_DEBUG_ENABLED
2084 ||
2085 ( (jtag_csr_write_enable == `TRUE)
2086 && (jtag_csr == `LM32_CSR_ICC))
2087 `endif
2088 ;
2089 `endif
2090 `ifdef CFG_DCACHE_ENABLED
2091 assign dflush_x = ( (csr_write_enable_q_x == `TRUE)
2092 && (csr_x == `LM32_CSR_DCC))
2093 // Added by GSI: needed to flush cache after loading firmware per JTAG
2094 `ifdef CFG_HW_DEBUG_ENABLED
2095 ||
2096 ( (jtag_csr_write_enable == `TRUE)
2097 && (jtag_csr == `LM32_CSR_DCC))
2098 `endif
2099 ;
2100 `endif
2101
2102 // Extract CSR index
2103 assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
2104
2105 // CSR reads
2106 always @(*)
2107 begin
2108 case (csr_x)
2109 `ifdef CFG_INTERRUPTS_ENABLED
2110 `LM32_CSR_IE,
2111 `LM32_CSR_IM,
2112 `LM32_CSR_IP: csr_read_data_x = interrupt_csr_read_data_x;
2113 `endif
2114 `ifdef CFG_CYCLE_COUNTER_ENABLED
2115 `LM32_CSR_CC: csr_read_data_x = cc;
2116 `endif
2117 `LM32_CSR_CFG: csr_read_data_x = cfg;
2118 `LM32_CSR_EBA: csr_read_data_x = {eba, 8'h00};
2119 `ifdef CFG_DEBUG_ENABLED
2120 `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
2121 `endif
2122 `ifdef CFG_JTAG_UART_ENABLED
2123 `LM32_CSR_JTX: csr_read_data_x = jtx_csr_read_data;
2124 `LM32_CSR_JRX: csr_read_data_x = jrx_csr_read_data;
2125 `endif
2126 `LM32_CSR_CFG2: csr_read_data_x = cfg2;
2127
2128 default: csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
2129 endcase
2130 end
2131
2132 /////////////////////////////////////////////////////
2133 // Sequential Logic
2134 /////////////////////////////////////////////////////
2135
2136 // Exception Base Address (EBA) CSR
2137 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2138 begin
2139 if (rst_i == `TRUE)
2140 eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
2141 else
2142 begin
2143 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
2144 eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
2145 `ifdef CFG_HW_DEBUG_ENABLED
2146 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
2147 eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
2148 `endif
2149 end
2150 end
2151
2152 `ifdef CFG_DEBUG_ENABLED
2153 // Debug Exception Base Address (DEBA) CSR
2154 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2155 begin
2156 if (rst_i == `TRUE)
2157 deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
2158 else
2159 begin
2160 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
2161 deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
2162 `ifdef CFG_HW_DEBUG_ENABLED
2163 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
2164 deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
2165 `endif
2166 end
2167 end
2168 `endif
2169
2170 // Cycle Counter (CC) CSR
2171 `ifdef CFG_CYCLE_COUNTER_ENABLED
2172 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2173 begin
2174 if (rst_i == `TRUE)
2175 cc <= {`LM32_WORD_WIDTH{1'b0}};
2176 else
2177 cc <= cc + 1'b1;
2178 end
2179 `endif
2180
2181 `ifdef CFG_BUS_ERRORS_ENABLED
2182 // Watch for data bus errors
2183 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2184 begin
2185 if (rst_i == `TRUE)
2186 data_bus_error_seen <= `FALSE;
2187 else
2188 begin
2189 // Set flag when bus error is detected
2190 if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
2191 data_bus_error_seen <= `TRUE;
2192 // Clear flag when exception is taken
2193 if ((exception_m == `TRUE) && (kill_m == `FALSE))
2194 data_bus_error_seen <= `FALSE;
2195 end
2196 end
2197 `endif
2198
2199 `ifdef CFG_EXTERNAL_BREAK_ENABLED
2200 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2201 begin
2202 if (rst_i == `TRUE)
2203 ext_break_r <= `FALSE;
2204 else
2205 begin
2206 if (ext_break == `TRUE)
2207 ext_break_r <= `TRUE;
2208 if (debug_exception_q_w == `TRUE)
2209 ext_break_r <= `FALSE;
2210 end
2211 end
2212 `endif
2213
2214 // Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not
2215
2216 `ifdef CFG_ICACHE_ENABLED
2217 `ifdef CFG_DCACHE_ENABLED
2218 always @(*)
2219 begin
2220 if ( (icache_refill_request == `TRUE)
2221 || (dcache_refill_request == `TRUE)
2222 )
2223 valid_a = `FALSE;
2224 else if ( (icache_restart_request == `TRUE)
2225 || (dcache_restart_request == `TRUE)
2226 )
2227 valid_a = `TRUE;
2228 else
2229 valid_a = !icache_refilling && !dcache_refilling;
2230 end
2231 `else
2232 always @(*)
2233 begin
2234 if (icache_refill_request == `TRUE)
2235 valid_a = `FALSE;
2236 else if (icache_restart_request == `TRUE)
2237 valid_a = `TRUE;
2238 else
2239 valid_a = !icache_refilling;
2240 end
2241 `endif
2242 `else
2243 `ifdef CFG_DCACHE_ENABLED
2244 always @(*)
2245 begin
2246 if (dcache_refill_request == `TRUE)
2247 valid_a = `FALSE;
2248 else if (dcache_restart_request == `TRUE)
2249 valid_a = `TRUE;
2250 else
2251 valid_a = !dcache_refilling;
2252 end
2253 `endif
2254 `endif
2255
2256 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2257 begin
2258 if (rst_i == `TRUE)
2259 begin
2260 valid_f <= `FALSE;
2261 valid_d <= `FALSE;
2262 valid_x <= `FALSE;
2263 valid_m <= `FALSE;
2264 valid_w <= `FALSE;
2265 end
2266 else
2267 begin
2268 if ((kill_f == `TRUE) || (stall_a == `FALSE))
2269 `ifdef LM32_CACHE_ENABLED
2270 valid_f <= valid_a;
2271 `else
2272 valid_f <= `TRUE;
2273 `endif
2274 else if (stall_f == `FALSE)
2275 valid_f <= `FALSE;
2276
2277 if (kill_d == `TRUE)
2278 valid_d <= `FALSE;
2279 else if (stall_f == `FALSE)
2280 valid_d <= valid_f & !kill_f;
2281 else if (stall_d == `FALSE)
2282 valid_d <= `FALSE;
2283
2284 if (stall_d == `FALSE)
2285 valid_x <= valid_d & !kill_d;
2286 else if (kill_x == `TRUE)
2287 valid_x <= `FALSE;
2288 else if (stall_x == `FALSE)
2289 valid_x <= `FALSE;
2290
2291 if (kill_m == `TRUE)
2292 valid_m <= `FALSE;
2293 else if (stall_x == `FALSE)
2294 valid_m <= valid_x & !kill_x;
2295 else if (stall_m == `FALSE)
2296 valid_m <= `FALSE;
2297
2298 if (stall_m == `FALSE)
2299 valid_w <= valid_m & !kill_m;
2300 else
2301 valid_w <= `FALSE;
2302 end
2303 end
2304
2305 // Microcode pipeline registers
2306 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2307 begin
2308 if (rst_i == `TRUE)
2309 begin
2310 `ifdef CFG_USER_ENABLED
2311 user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};
2312 `endif
2313 operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
2314 operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
2315 store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
2316 branch_target_x <= {`LM32_PC_WIDTH{1'b0}};
2317 x_result_sel_csr_x <= `FALSE;
2318 `ifdef LM32_MC_ARITHMETIC_ENABLED
2319 x_result_sel_mc_arith_x <= `FALSE;
2320 `endif
2321 `ifdef LM32_NO_BARREL_SHIFT
2322 x_result_sel_shift_x <= `FALSE;
2323 `endif
2324 `ifdef CFG_SIGN_EXTEND_ENABLED
2325 x_result_sel_sext_x <= `FALSE;
2326 `endif
2327 x_result_sel_logic_x <= `FALSE;
2328 `ifdef CFG_USER_ENABLED
2329 x_result_sel_user_x <= `FALSE;
2330 `endif
2331 x_result_sel_add_x <= `FALSE;
2332 m_result_sel_compare_x <= `FALSE;
2333 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2334 m_result_sel_shift_x <= `FALSE;
2335 `endif
2336 w_result_sel_load_x <= `FALSE;
2337 `ifdef CFG_PL_MULTIPLY_ENABLED
2338 w_result_sel_mul_x <= `FALSE;
2339 `endif
2340 x_bypass_enable_x <= `FALSE;
2341 m_bypass_enable_x <= `FALSE;
2342 write_enable_x <= `FALSE;
2343 write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
2344 csr_x <= {`LM32_CSR_WIDTH{1'b0}};
2345 load_x <= `FALSE;
2346 store_x <= `FALSE;
2347 size_x <= {`LM32_SIZE_WIDTH{1'b0}};
2348 sign_extend_x <= `FALSE;
2349 adder_op_x <= `FALSE;
2350 adder_op_x_n <= `FALSE;
2351 logic_op_x <= 4'h0;
2352 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2353 direction_x <= `FALSE;
2354 `endif
2355 `ifdef CFG_ROTATE_ENABLED
2356 rotate_x <= `FALSE;
2357
2358 `endif
2359 branch_x <= `FALSE;
2360 branch_predict_x <= `FALSE;
2361 branch_predict_taken_x <= `FALSE;
2362 condition_x <= `LM32_CONDITION_U1;
2363 `ifdef CFG_DEBUG_ENABLED
2364 break_x <= `FALSE;
2365 `endif
2366 scall_x <= `FALSE;
2367 eret_x <= `FALSE;
2368 `ifdef CFG_DEBUG_ENABLED
2369 bret_x <= `FALSE;
2370 `endif
2371 `ifdef CFG_BUS_ERRORS_ENABLED
2372 bus_error_x <= `FALSE;
2373 data_bus_error_exception_m <= `FALSE;
2374 `endif
2375 csr_write_enable_x <= `FALSE;
2376 operand_m <= {`LM32_WORD_WIDTH{1'b0}};
2377 branch_target_m <= {`LM32_PC_WIDTH{1'b0}};
2378 m_result_sel_compare_m <= `FALSE;
2379 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2380 m_result_sel_shift_m <= `FALSE;
2381 `endif
2382 w_result_sel_load_m <= `FALSE;
2383 `ifdef CFG_PL_MULTIPLY_ENABLED
2384 w_result_sel_mul_m <= `FALSE;
2385 `endif
2386 m_bypass_enable_m <= `FALSE;
2387 branch_m <= `FALSE;
2388 branch_predict_m <= `FALSE;
2389 branch_predict_taken_m <= `FALSE;
2390 exception_m <= `FALSE;
2391 load_m <= `FALSE;
2392 store_m <= `FALSE;
2393 write_enable_m <= `FALSE;
2394 write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
2395 condition_met_m <= `FALSE;
2396 `ifdef CFG_DCACHE_ENABLED
2397 dflush_m <= `FALSE;
2398 `endif
2399 `ifdef CFG_DEBUG_ENABLED
2400 debug_exception_m <= `FALSE;
2401 non_debug_exception_m <= `FALSE;
2402 `endif
2403 operand_w <= {`LM32_WORD_WIDTH{1'b0}};
2404 w_result_sel_load_w <= `FALSE;
2405 `ifdef CFG_PL_MULTIPLY_ENABLED
2406 w_result_sel_mul_w <= `FALSE;
2407 `endif
2408 write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};
2409 write_enable_w <= `FALSE;
2410 `ifdef CFG_DEBUG_ENABLED
2411 debug_exception_w <= `FALSE;
2412 non_debug_exception_w <= `FALSE;
2413 `else
2414 exception_w <= `FALSE;
2415 `endif
2416 `ifdef CFG_BUS_ERRORS_ENABLED
2417 memop_pc_w <= {`LM32_PC_WIDTH{1'b0}};
2418 `endif
2419 end
2420 else
2421 begin
2422 // D/X stage registers
2423
2424 if (stall_x == `FALSE)
2425 begin
2426 `ifdef CFG_USER_ENABLED
2427 user_opcode <= user_opcode_d;
2428 `endif
2429 operand_0_x <= d_result_0;
2430 operand_1_x <= d_result_1;
2431 store_operand_x <= bypass_data_1;
2432 branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;
2433 x_result_sel_csr_x <= x_result_sel_csr_d;
2434 `ifdef LM32_MC_ARITHMETIC_ENABLED
2435 x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
2436 `endif
2437 `ifdef LM32_NO_BARREL_SHIFT
2438 x_result_sel_shift_x <= x_result_sel_shift_d;
2439 `endif
2440 `ifdef CFG_SIGN_EXTEND_ENABLED
2441 x_result_sel_sext_x <= x_result_sel_sext_d;
2442 `endif
2443 x_result_sel_logic_x <= x_result_sel_logic_d;
2444 `ifdef CFG_USER_ENABLED
2445 x_result_sel_user_x <= x_result_sel_user_d;
2446 `endif
2447 x_result_sel_add_x <= x_result_sel_add_d;
2448 m_result_sel_compare_x <= m_result_sel_compare_d;
2449 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2450 m_result_sel_shift_x <= m_result_sel_shift_d;
2451 `endif
2452 w_result_sel_load_x <= w_result_sel_load_d;
2453 `ifdef CFG_PL_MULTIPLY_ENABLED
2454 w_result_sel_mul_x <= w_result_sel_mul_d;
2455 `endif
2456 x_bypass_enable_x <= x_bypass_enable_d;
2457 m_bypass_enable_x <= m_bypass_enable_d;
2458 load_x <= load_d;
2459 store_x <= store_d;
2460 branch_x <= branch_d;
2461 branch_predict_x <= branch_predict_d;
2462 branch_predict_taken_x <= branch_predict_taken_d;
2463 write_idx_x <= write_idx_d;
2464 csr_x <= csr_d;
2465 size_x <= size_d;
2466 sign_extend_x <= sign_extend_d;
2467 adder_op_x <= adder_op_d;
2468 adder_op_x_n <= ~adder_op_d;
2469 logic_op_x <= logic_op_d;
2470 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2471 direction_x <= direction_d;
2472 `endif
2473 `ifdef CFG_ROTATE_ENABLED
2474 rotate_x <= rotate_d;
2475 `endif
2476 condition_x <= condition_d;
2477 csr_write_enable_x <= csr_write_enable_d;
2478 `ifdef CFG_DEBUG_ENABLED
2479 break_x <= break_d;
2480 `endif
2481 scall_x <= scall_d;
2482 `ifdef CFG_BUS_ERRORS_ENABLED
2483 bus_error_x <= bus_error_d;
2484 `endif
2485 eret_x <= eret_d;
2486 `ifdef CFG_DEBUG_ENABLED
2487 bret_x <= bret_d;
2488 `endif
2489 write_enable_x <= write_enable_d;
2490 end
2491
2492 // X/M stage registers
2493
2494 if (stall_m == `FALSE)
2495 begin
2496 operand_m <= x_result;
2497 m_result_sel_compare_m <= m_result_sel_compare_x;
2498 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2499 m_result_sel_shift_m <= m_result_sel_shift_x;
2500 `endif
2501 if (exception_x == `TRUE)
2502 begin
2503 w_result_sel_load_m <= `FALSE;
2504 `ifdef CFG_PL_MULTIPLY_ENABLED
2505 w_result_sel_mul_m <= `FALSE;
2506 `endif
2507 end
2508 else
2509 begin
2510 w_result_sel_load_m <= w_result_sel_load_x;
2511 `ifdef CFG_PL_MULTIPLY_ENABLED
2512 w_result_sel_mul_m <= w_result_sel_mul_x;
2513 `endif
2514 end
2515 m_bypass_enable_m <= m_bypass_enable_x;
2516 load_m <= load_x;
2517 store_m <= store_x;
2518 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
2519 branch_m <= branch_x && !branch_taken_x;
2520 `else
2521 branch_m <= branch_x;
2522 branch_predict_m <= branch_predict_x;
2523 branch_predict_taken_m <= branch_predict_taken_x;
2524 `endif
2525 `ifdef CFG_DEBUG_ENABLED
2526 // Data bus errors are generated by the wishbone and are
2527 // made known to the processor only in next cycle (as a
2528 // non-debug exception). A break instruction can be seen
2529 // in same cycle (causing a debug exception). Handle non
2530 // -debug exception first!
2531 if (non_debug_exception_x == `TRUE)
2532 write_idx_m <= `LM32_EA_REG;
2533 else if (debug_exception_x == `TRUE)
2534 write_idx_m <= `LM32_BA_REG;
2535 else
2536 write_idx_m <= write_idx_x;
2537 `else
2538 if (exception_x == `TRUE)
2539 write_idx_m <= `LM32_EA_REG;
2540 else
2541 write_idx_m <= write_idx_x;
2542 `endif
2543 condition_met_m <= condition_met_x;
2544 `ifdef CFG_DEBUG_ENABLED
2545 if (exception_x == `TRUE)
2546 if ((dc_re == `TRUE)
2547 `ifdef CFG_ALTERNATE_EBA
2548 || (at_debug == `TRUE)
2549 `endif
2550
2551 || ((debug_exception_x == `TRUE)
2552 && (non_debug_exception_x == `FALSE)))
2553 branch_target_m <= {deba, eid_x, {3{1'b0}}};
2554 else
2555 branch_target_m <= {eba, eid_x, {3{1'b0}}};
2556 else
2557 branch_target_m <= branch_target_x;
2558 `else
2559 branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
2560 `endif
2561 `ifdef CFG_TRACE_ENABLED
2562 eid_m <= eid_x;
2563 `endif
2564 `ifdef CFG_DCACHE_ENABLED
2565 dflush_m <= dflush_x;
2566 `endif
2567 eret_m <= eret_q_x;
2568 `ifdef CFG_DEBUG_ENABLED
2569 bret_m <= bret_q_x;
2570 `endif
2571 write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;
2572 `ifdef CFG_DEBUG_ENABLED
2573 debug_exception_m <= debug_exception_x;
2574 non_debug_exception_m <= non_debug_exception_x;
2575 `endif
2576 end
2577
2578 // State changing regs
2579 if (stall_m == `FALSE)
2580 begin
2581 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
2582 exception_m <= `TRUE;
2583 else
2584 exception_m <= `FALSE;
2585 `ifdef CFG_BUS_ERRORS_ENABLED
2586 data_bus_error_exception_m <= (data_bus_error_exception == `TRUE)
2587 `ifdef CFG_DEBUG_ENABLED
2588 && (reset_exception == `FALSE)
2589 `endif
2590 ;
2591 `endif
2592 end
2593
2594 // M/W stage registers
2595 `ifdef CFG_BUS_ERRORS_ENABLED
2596 operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
2597 `else
2598 operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
2599 `endif
2600 w_result_sel_load_w <= w_result_sel_load_m;
2601 `ifdef CFG_PL_MULTIPLY_ENABLED
2602 w_result_sel_mul_w <= w_result_sel_mul_m;
2603 `endif
2604 write_idx_w <= write_idx_m;
2605 `ifdef CFG_TRACE_ENABLED
2606 eid_w <= eid_m;
2607 eret_w <= eret_m;
2608 `ifdef CFG_DEBUG_ENABLED
2609 bret_w <= bret_m;
2610 `endif
2611 `endif
2612 write_enable_w <= write_enable_m;
2613 `ifdef CFG_DEBUG_ENABLED
2614 debug_exception_w <= debug_exception_m;
2615 non_debug_exception_w <= non_debug_exception_m;
2616 `else
2617 exception_w <= exception_m;
2618 `endif
2619 `ifdef CFG_BUS_ERRORS_ENABLED
2620 if ( (stall_m == `FALSE)
2621 && (data_bus_error_exception == `FALSE)
2622 && ( (load_q_m == `TRUE)
2623 || (store_q_m == `TRUE)
2624 )
2625 )
2626 memop_pc_w <= pc_m;
2627 `endif
2628 end
2629 end
2630
2631 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
2632 // Buffer data read from register file, in case a stall occurs, and watch for
2633 // any writes to the modified registers
2634 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2635 begin
2636 if (rst_i == `TRUE)
2637 begin
2638 use_buf <= `FALSE;
2639 reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
2640 reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
2641 end
2642 else
2643 begin
2644 if (stall_d == `FALSE)
2645 use_buf <= `FALSE;
2646 else if (use_buf == `FALSE)
2647 begin
2648 reg_data_buf_0 <= reg_data_live_0;
2649 reg_data_buf_1 <= reg_data_live_1;
2650 use_buf <= `TRUE;
2651 end
2652 if (reg_write_enable_q_w == `TRUE)
2653 begin
2654 if (write_idx_w == read_idx_0_d)
2655 reg_data_buf_0 <= w_result;
2656 if (write_idx_w == read_idx_1_d)
2657 reg_data_buf_1 <= w_result;
2658 end
2659 end
2660 end
2661 `endif
2662
2663 `ifdef LM32_EBR_REGISTER_FILE
2664 `else
2665 // Register file write port
2666 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2667 begin
2668 if (rst_i == `TRUE) begin
2669 registers[0] <= {`LM32_WORD_WIDTH{1'b0}};
2670 registers[1] <= {`LM32_WORD_WIDTH{1'b0}};
2671 registers[2] <= {`LM32_WORD_WIDTH{1'b0}};
2672 registers[3] <= {`LM32_WORD_WIDTH{1'b0}};
2673 registers[4] <= {`LM32_WORD_WIDTH{1'b0}};
2674 registers[5] <= {`LM32_WORD_WIDTH{1'b0}};
2675 registers[6] <= {`LM32_WORD_WIDTH{1'b0}};
2676 registers[7] <= {`LM32_WORD_WIDTH{1'b0}};
2677 registers[8] <= {`LM32_WORD_WIDTH{1'b0}};
2678 registers[9] <= {`LM32_WORD_WIDTH{1'b0}};
2679 registers[10] <= {`LM32_WORD_WIDTH{1'b0}};
2680 registers[11] <= {`LM32_WORD_WIDTH{1'b0}};
2681 registers[12] <= {`LM32_WORD_WIDTH{1'b0}};
2682 registers[13] <= {`LM32_WORD_WIDTH{1'b0}};
2683 registers[14] <= {`LM32_WORD_WIDTH{1'b0}};
2684 registers[15] <= {`LM32_WORD_WIDTH{1'b0}};
2685 registers[16] <= {`LM32_WORD_WIDTH{1'b0}};
2686 registers[17] <= {`LM32_WORD_WIDTH{1'b0}};
2687 registers[18] <= {`LM32_WORD_WIDTH{1'b0}};
2688 registers[19] <= {`LM32_WORD_WIDTH{1'b0}};
2689 registers[20] <= {`LM32_WORD_WIDTH{1'b0}};
2690 registers[21] <= {`LM32_WORD_WIDTH{1'b0}};
2691 registers[22] <= {`LM32_WORD_WIDTH{1'b0}};
2692 registers[23] <= {`LM32_WORD_WIDTH{1'b0}};
2693 registers[24] <= {`LM32_WORD_WIDTH{1'b0}};
2694 registers[25] <= {`LM32_WORD_WIDTH{1'b0}};
2695 registers[26] <= {`LM32_WORD_WIDTH{1'b0}};
2696 registers[27] <= {`LM32_WORD_WIDTH{1'b0}};
2697 registers[28] <= {`LM32_WORD_WIDTH{1'b0}};
2698 registers[29] <= {`LM32_WORD_WIDTH{1'b0}};
2699 registers[30] <= {`LM32_WORD_WIDTH{1'b0}};
2700 registers[31] <= {`LM32_WORD_WIDTH{1'b0}};
2701 end
2702 else begin
2703 if (reg_write_enable_q_w == `TRUE)
2704 registers[write_idx_w] <= w_result;
2705 end
2706 end
2707 `endif
2708
2709 `ifdef CFG_TRACE_ENABLED
2710 // PC tracing logic
2711 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2712 begin
2713 if (rst_i == `TRUE)
2714 begin
2715 trace_pc_valid <= `FALSE;
2716 trace_pc <= {`LM32_PC_WIDTH{1'b0}};
2717 trace_exception <= `FALSE;
2718 trace_eid <= `LM32_EID_RESET;
2719 trace_eret <= `FALSE;
2720 `ifdef CFG_DEBUG_ENABLED
2721 trace_bret <= `FALSE;
2722 `endif
2723 pc_c <= `CFG_EBA_RESET/4;
2724 end
2725 else
2726 begin
2727 trace_pc_valid <= `FALSE;
2728 // Has an exception occured
2729 `ifdef CFG_DEBUG_ENABLED
2730 if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
2731 `else
2732 if (exception_q_w == `TRUE)
2733 `endif
2734 begin
2735 trace_exception <= `TRUE;
2736 trace_pc_valid <= `TRUE;
2737 trace_pc <= pc_w;
2738 trace_eid <= eid_w;
2739 end
2740 else
2741 trace_exception <= `FALSE;
2742
2743 if ((valid_w == `TRUE) && (!kill_w))
2744 begin
2745 // An instruction is commiting. Determine if it is non-sequential
2746 if (pc_c + 1'b1 != pc_w)
2747 begin
2748 // Non-sequential instruction
2749 trace_pc_valid <= `TRUE;
2750 trace_pc <= pc_w;
2751 end
2752 // Record PC so we can determine if next instruction is sequential or not
2753 pc_c <= pc_w;
2754 // Indicate if it was an eret/bret instruction
2755 trace_eret <= eret_w;
2756 `ifdef CFG_DEBUG_ENABLED
2757 trace_bret <= bret_w;
2758 `endif
2759 end
2760 else
2761 begin
2762 trace_eret <= `FALSE;
2763 `ifdef CFG_DEBUG_ENABLED
2764 trace_bret <= `FALSE;
2765 `endif
2766 end
2767 end
2768 end
2769 `endif
2770
2771 endmodule