verilog/lm32/lm32_dp_ram.v

   1 module lm32_dp_ram(
   2         clk_i,
   3         rst_i,
   4         we_i,
   5         waddr_i,
   6         wdata_i,
   7         raddr_i,
   8         rdata_o);
   9
  10 parameter addr_width = 32;
  11 parameter addr_depth = 1024;
  12 parameter data_width = 8;
  13
  14 input clk_i;
  15 input rst_i;
  16 input we_i;
  17 input [addr_width-1:0] waddr_i;
  18 input [data_width-1:0] wdata_i;
  19 input [addr_width-1:0] raddr_i;
  20 output [data_width-1:0] rdata_o;
  21
  22 reg [data_width-1:0] ram[addr_depth-1:0];
  23
  24 reg [addr_width-1:0] raddr_r;
  25 assign rdata_o = ram[raddr_r];
  26
  27 always @ (posedge clk_i)
  28 begin
  29         if (we_i)
  30                 ram[waddr_i] <= wdata_i;
  31         raddr_r <= raddr_i;
  32 end
  33
  34 endmodule
  35