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38 // Project : LatticeMico32
39 // File : lm32_load_store_unit.v
40 // Title : Load and store unit
41 // Dependencies : lm32_include.v
44 // Version : 7.0SP2, 3.0
47 // : Instead of disallowing an instruction cache miss on a data cache
48 // : miss, both can now occur at the same time. If both occur at same
49 // : time, then restart address is the address of instruction that
50 // : caused data cache miss.
52 // : EBRs use SYNC resets instead of ASYNC resets.
54 // : Support for new non-cacheable Data Memory that is accessible by
55 // : the data port and has a one cycle access latency.
59 // : Bug fix: Inline memory is correctly generated if it is not a
61 // =============================================================================
63 `include "lm32_include.v"
65 /////////////////////////////////////////////////////
67 /////////////////////////////////////////////////////
69 module lm32_load_store_unit (
70 // ----- Inputs -------
92 `ifdef CFG_DCACHE_ENABLED
95 `ifdef CFG_IROM_ENABLED
103 // ----- Outputs -------
105 `ifdef CFG_DCACHE_ENABLED
106 dcache_refill_request,
107 dcache_restart_request,
108 dcache_stall_request,
111 `ifdef CFG_IROM_ENABLED
115 irom_stall_request_x,
131 /////////////////////////////////////////////////////
133 /////////////////////////////////////////////////////
135 parameter associativity = 1; // Associativity of the cache (Number of ways)
136 parameter sets = 512; // Number of sets
137 parameter bytes_per_line = 16; // Number of bytes per cache line
138 parameter base_address = 0; // Base address of cachable memory
139 parameter limit = 0; // Limit (highest address) of cachable memory
141 // For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
142 localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
143 localparam addr_offset_lsb = 2;
144 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
146 /////////////////////////////////////////////////////
148 /////////////////////////////////////////////////////
150 input clk_i; // Clock
151 input rst_i; // Reset
153 input stall_a; // A stage stall
154 input stall_x; // X stage stall
155 input stall_m; // M stage stall
156 input kill_x; // Kill instruction in X stage
157 input kill_m; // Kill instruction in M stage
158 input exception_m; // An exception occured in the M stage
160 input [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
161 input [`LM32_WORD_RNG] load_store_address_x; // X stage load/store address
162 input [`LM32_WORD_RNG] load_store_address_m; // M stage load/store address
163 input [1:0] load_store_address_w; // W stage load/store address (only least two significant bits are needed)
164 input load_x; // Load instruction in X stage
165 input store_x; // Store instruction in X stage
166 input load_q_x; // Load instruction in X stage
167 input store_q_x; // Store instruction in X stage
168 input load_q_m; // Load instruction in M stage
169 input store_q_m; // Store instruction in M stage
170 input sign_extend_x; // Whether load instruction in X stage should sign extend or zero extend
171 input [`LM32_SIZE_RNG] size_x; // Size of load or store (byte, hword, word)
173 `ifdef CFG_DCACHE_ENABLED
174 input dflush; // Flush the data cache
177 `ifdef CFG_IROM_ENABLED
178 input [`LM32_WORD_RNG] irom_data_m; // Data from Instruction-ROM
181 input [`LM32_WORD_RNG] d_dat_i; // Data Wishbone interface read data
182 input d_ack_i; // Data Wishbone interface acknowledgement
183 input d_err_i; // Data Wishbone interface error
184 input d_rty_i; // Data Wishbone interface retry
186 /////////////////////////////////////////////////////
188 /////////////////////////////////////////////////////
190 `ifdef CFG_DCACHE_ENABLED
191 output dcache_refill_request; // Request to refill data cache
192 wire dcache_refill_request;
193 output dcache_restart_request; // Request to restart the instruction that caused a data cache miss
194 wire dcache_restart_request;
195 output dcache_stall_request; // Data cache stall request
196 wire dcache_stall_request;
197 output dcache_refilling;
198 wire dcache_refilling;
201 `ifdef CFG_IROM_ENABLED
202 output irom_store_data_m; // Store data to Instruction ROM
203 wire [`LM32_WORD_RNG] irom_store_data_m;
204 output [`LM32_WORD_RNG] irom_address_xm; // Load/store address to Instruction ROM
205 wire [`LM32_WORD_RNG] irom_address_xm;
206 output irom_we_xm; // Write-enable of 2nd port of Instruction ROM
208 output irom_stall_request_x; // Stall instruction in D stage
209 wire irom_stall_request_x;
212 output [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
213 reg [`LM32_WORD_RNG] load_data_w;
214 output stall_wb_load; // Request to stall pipeline due to a load from the Wishbone interface
217 output [`LM32_WORD_RNG] d_dat_o; // Data Wishbone interface write data
218 reg [`LM32_WORD_RNG] d_dat_o;
219 output [`LM32_WORD_RNG] d_adr_o; // Data Wishbone interface address
220 reg [`LM32_WORD_RNG] d_adr_o;
221 output d_cyc_o; // Data Wishbone interface cycle
223 output [`LM32_BYTE_SELECT_RNG] d_sel_o; // Data Wishbone interface byte select
224 reg [`LM32_BYTE_SELECT_RNG] d_sel_o;
225 output d_stb_o; // Data Wishbone interface strobe
227 output d_we_o; // Data Wishbone interface write enable
229 output [`LM32_CTYPE_RNG] d_cti_o; // Data Wishbone interface cycle type
230 reg [`LM32_CTYPE_RNG] d_cti_o;
231 output d_lock_o; // Date Wishbone interface lock bus
233 output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type
234 wire [`LM32_BTYPE_RNG] d_bte_o;
236 /////////////////////////////////////////////////////
237 // Internal nets and registers
238 /////////////////////////////////////////////////////
240 // Microcode pipeline registers - See inputs for description
241 reg [`LM32_SIZE_RNG] size_m;
242 reg [`LM32_SIZE_RNG] size_w;
245 reg [`LM32_WORD_RNG] store_data_x;
246 reg [`LM32_WORD_RNG] store_data_m;
247 reg [`LM32_BYTE_SELECT_RNG] byte_enable_x;
248 reg [`LM32_BYTE_SELECT_RNG] byte_enable_m;
249 wire [`LM32_WORD_RNG] data_m;
250 reg [`LM32_WORD_RNG] data_w;
252 `ifdef CFG_DCACHE_ENABLED
253 wire dcache_select_x; // Select data cache to load from / store to
255 wire [`LM32_WORD_RNG] dcache_data_m; // Data read from cache
256 wire [`LM32_WORD_RNG] dcache_refill_address; // Address to refill data cache from
257 reg dcache_refill_ready; // Indicates the next word of refill data is ready
258 wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
259 wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
260 wire last_word; // Indicates if this is the last word in the cache line
261 wire [`LM32_WORD_RNG] first_address; // First cache refill address
263 `ifdef CFG_DRAM_ENABLED
264 wire dram_select_x; // Select data RAM to load from / store to
266 reg dram_bypass_en; // RAW in data RAM; read latched (bypass) value rather than value from memory
267 reg [`LM32_WORD_RNG] dram_bypass_data; // Latched value of store'd data to data RAM
268 wire [`LM32_WORD_RNG] dram_data_out; // Data read from data RAM
269 wire [`LM32_WORD_RNG] dram_data_m; // Data read from data RAM: bypass value or value from memory
270 wire [`LM32_WORD_RNG] dram_store_data_m; // Data to write to RAM
272 wire wb_select_x; // Select Wishbone to load from / store to
273 `ifdef CFG_IROM_ENABLED
274 wire irom_select_x; // Select instruction ROM to load from / store to
278 reg [`LM32_WORD_RNG] wb_data_m; // Data read from Wishbone
279 reg wb_load_complete; // Indicates when a Wishbone load is complete
281 /////////////////////////////////////////////////////
283 /////////////////////////////////////////////////////
285 `include "lm32_functions.v"
287 /////////////////////////////////////////////////////
289 /////////////////////////////////////////////////////
291 `ifdef CFG_DRAM_ENABLED
295 // ----- Parameters -------
296 .pmi_family (`LATTICE_FAMILY),
298 //.pmi_addr_depth_a (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
299 //.pmi_addr_width_a ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
300 //.pmi_data_width_a (`LM32_WORD_WIDTH),
301 //.pmi_addr_depth_b (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
302 //.pmi_addr_width_b ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
303 //.pmi_data_width_b (`LM32_WORD_WIDTH),
305 .pmi_addr_depth_a (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
306 .pmi_addr_width_a (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
307 .pmi_data_width_a (`LM32_WORD_WIDTH),
308 .pmi_addr_depth_b (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
309 .pmi_addr_width_b (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
310 .pmi_data_width_b (`LM32_WORD_WIDTH),
312 .pmi_regmode_a ("noreg"),
313 .pmi_regmode_b ("noreg"),
315 .pmi_resetmode ("sync"),
316 .pmi_init_file (`CFG_DRAM_INIT_FILE),
317 .pmi_init_file_format (`CFG_DRAM_INIT_FILE_FORMAT),
318 .module_type ("pmi_ram_dp_true")
321 // ----- Inputs -------
326 .DataInA ({32{1'b0}}),
327 .DataInB (dram_store_data_m),
328 .AddressA (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
329 .AddressB (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
330 // .ClockEnA (!stall_x & (load_x | store_x)),
331 .ClockEnA (!stall_x),
332 .ClockEnB (!stall_m),
334 .WrB (store_q_m & dram_select_m),
335 // ----- Outputs -------
340 /*----------------------------------------------------------------------
341 EBRs cannot perform reads from location 'written to' on the same clock
342 edge. Therefore bypass logic is required to latch the store'd value
343 and use it for the load (instead of value from memory).
344 ----------------------------------------------------------------------*/
345 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
348 dram_bypass_en <= `FALSE;
349 dram_bypass_data <= 0;
353 if (stall_x == `FALSE)
354 dram_bypass_data <= dram_store_data_m;
356 if ( (stall_m == `FALSE)
357 && (stall_x == `FALSE)
358 && (store_q_m == `TRUE)
359 && ( (load_x == `TRUE)
360 || (store_x == `TRUE)
362 && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2])
364 dram_bypass_en <= `TRUE;
366 if ( (dram_bypass_en == `TRUE)
367 && (stall_x == `FALSE)
369 dram_bypass_en <= `FALSE;
372 assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out;
375 `ifdef CFG_DCACHE_ENABLED
378 .associativity (associativity),
380 .bytes_per_line (bytes_per_line),
381 .base_address (base_address),
384 // ----- Inputs -----
390 .address_x (load_store_address_x),
391 .address_m (load_store_address_m),
392 .load_q_m (load_q_m & dcache_select_m),
393 .store_q_m (store_q_m & dcache_select_m),
394 .store_data (store_data_m),
395 .store_byte_select (byte_enable_m & {4{dcache_select_m}}),
396 .refill_ready (dcache_refill_ready),
397 .refill_data (wb_data_m),
399 // ----- Outputs -----
400 .stall_request (dcache_stall_request),
401 .restart_request (dcache_restart_request),
402 .refill_request (dcache_refill_request),
403 .refill_address (dcache_refill_address),
404 .refilling (dcache_refilling),
405 .load_data (dcache_data_m)
409 /////////////////////////////////////////////////////
410 // Combinational Logic
411 /////////////////////////////////////////////////////
413 // Select where data should be loaded from / stored to
414 `ifdef CFG_DRAM_ENABLED
415 assign dram_select_x = (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS)
416 && (load_store_address_x <= `CFG_DRAM_LIMIT);
419 `ifdef CFG_IROM_ENABLED
420 assign irom_select_x = (load_store_address_x >= `CFG_IROM_BASE_ADDRESS)
421 && (load_store_address_x <= `CFG_IROM_LIMIT);
424 `ifdef CFG_DCACHE_ENABLED
425 assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS)
426 && (load_store_address_x <= `CFG_DCACHE_LIMIT)
427 `ifdef CFG_DRAM_ENABLED
428 && (dram_select_x == `FALSE)
430 `ifdef CFG_IROM_ENABLED
431 && (irom_select_x == `FALSE)
436 assign wb_select_x = `TRUE
437 `ifdef CFG_DCACHE_ENABLED
440 `ifdef CFG_DRAM_ENABLED
443 `ifdef CFG_IROM_ENABLED
448 // Make sure data to store is in correct byte lane
452 `LM32_SIZE_BYTE: store_data_x = {4{store_operand_x[7:0]}};
453 `LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}};
454 `LM32_SIZE_WORD: store_data_x = store_operand_x;
455 default: store_data_x = {`LM32_WORD_WIDTH{1'bx}};
459 // Generate byte enable accoring to size of load or store and address being accessed
462 casez ({size_x, load_store_address_x[1:0]})
463 {`LM32_SIZE_BYTE, 2'b11}: byte_enable_x = 4'b0001;
464 {`LM32_SIZE_BYTE, 2'b10}: byte_enable_x = 4'b0010;
465 {`LM32_SIZE_BYTE, 2'b01}: byte_enable_x = 4'b0100;
466 {`LM32_SIZE_BYTE, 2'b00}: byte_enable_x = 4'b1000;
467 {`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011;
468 {`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100;
469 {`LM32_SIZE_WORD, 2'b??}: byte_enable_x = 4'b1111;
470 default: byte_enable_x = 4'bxxxx;
474 `ifdef CFG_DRAM_ENABLED
475 // Only replace selected bytes
476 assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG];
477 assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG];
478 assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG];
479 assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG];
482 `ifdef CFG_IROM_ENABLED
483 // Only replace selected bytes
484 assign irom_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : irom_data_m[`LM32_BYTE_0_RNG];
485 assign irom_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : irom_data_m[`LM32_BYTE_1_RNG];
486 assign irom_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : irom_data_m[`LM32_BYTE_2_RNG];
487 assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : irom_data_m[`LM32_BYTE_3_RNG];
490 `ifdef CFG_IROM_ENABLED
491 // Instead of implementing a byte-addressable instruction ROM (for store byte instruction),
492 // a load-and-store architecture is used wherein a 32-bit value is loaded, the requisite
493 // byte is replaced, and the whole 32-bit value is written back
495 assign irom_address_xm = ((irom_select_m == `TRUE) && (store_q_m == `TRUE))
496 ? load_store_address_m
497 : load_store_address_x;
499 // All store instructions perform a write operation in the M stage
500 assign irom_we_xm = (irom_select_m == `TRUE)
501 && (store_q_m == `TRUE);
503 // A single port in instruction ROM is available to load-store unit for doing loads/stores.
504 // Since every store requires a load (in X stage) and then a store (in M stage), we cannot
505 // allow load (or store) instructions sequentially after the store instructions to proceed
506 // until the store instruction has vacated M stage (i.e., completed the store operation)
507 assign irom_stall_request_x = (irom_select_x == `TRUE)
508 && (store_q_x == `TRUE);
511 `ifdef CFG_DCACHE_ENABLED
512 `ifdef CFG_DRAM_ENABLED
513 `ifdef CFG_IROM_ENABLED
514 // WB + DC + DRAM + IROM
515 assign data_m = wb_select_m == `TRUE
517 : dram_select_m == `TRUE
519 : irom_select_m == `TRUE
524 assign data_m = wb_select_m == `TRUE
526 : dram_select_m == `TRUE
531 `ifdef CFG_IROM_ENABLED
533 assign data_m = wb_select_m == `TRUE
535 : irom_select_m == `TRUE
540 assign data_m = wb_select_m == `TRUE
546 `ifdef CFG_DRAM_ENABLED
547 `ifdef CFG_IROM_ENABLED
549 assign data_m = wb_select_m == `TRUE
551 : dram_select_m == `TRUE
556 assign data_m = wb_select_m == `TRUE
561 `ifdef CFG_IROM_ENABLED
563 assign data_m = wb_select_m == `TRUE
568 assign data_m = wb_data_m;
573 // Sub-word selection and sign/zero-extension for loads
576 casez ({size_w, load_store_address_w[1:0]})
577 {`LM32_SIZE_BYTE, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
578 {`LM32_SIZE_BYTE, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
579 {`LM32_SIZE_BYTE, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
580 {`LM32_SIZE_BYTE, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
581 {`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
582 {`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
583 {`LM32_SIZE_WORD, 2'b??}: load_data_w = data_w;
584 default: load_data_w = {`LM32_WORD_WIDTH{1'bx}};
588 // Unused/constant Wishbone signals
589 assign d_bte_o = `LM32_BTYPE_LINEAR;
591 `ifdef CFG_DCACHE_ENABLED
592 // Generate signal to indicate last word in cache line
594 case (bytes_per_line)
597 assign first_cycle_type = `LM32_CTYPE_END;
598 assign next_cycle_type = `LM32_CTYPE_END;
599 assign last_word = `TRUE;
600 assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00};
604 assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
605 assign next_cycle_type = `LM32_CTYPE_END;
606 assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
607 assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
611 assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
612 assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
613 assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
614 assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
620 /////////////////////////////////////////////////////
622 /////////////////////////////////////////////////////
624 // Data Wishbone interface
625 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
631 d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
632 d_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
633 d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
635 d_cti_o <= `LM32_CTYPE_END;
637 wb_data_m <= {`LM32_WORD_WIDTH{1'b0}};
638 wb_load_complete <= `FALSE;
639 stall_wb_load <= `FALSE;
640 `ifdef CFG_DCACHE_ENABLED
641 dcache_refill_ready <= `FALSE;
646 `ifdef CFG_DCACHE_ENABLED
647 // Refill ready should only be asserted for a single cycle
648 dcache_refill_ready <= `FALSE;
650 // Is a Wishbone cycle already in progress?
651 if (d_cyc_o == `TRUE)
653 // Is the cycle complete?
654 if ((d_ack_i == `TRUE) || (d_err_i == `TRUE))
656 `ifdef CFG_DCACHE_ENABLED
657 if ((dcache_refilling == `TRUE) && (!last_word))
659 // Fetch next word of cache line
660 d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
665 // Refill/access complete
670 `ifdef CFG_DCACHE_ENABLED
671 d_cti_o <= next_cycle_type;
672 // If we are performing a refill, indicate to cache next word of data is ready
673 dcache_refill_ready <= dcache_refilling;
675 // Register data read from Wishbone interface
676 wb_data_m <= d_dat_i;
677 // Don't set when stores complete - otherwise we'll deadlock if load in m stage
678 wb_load_complete <= !d_we_o;
680 // synthesis translate_off
681 if (d_err_i == `TRUE)
682 $display ("Data bus error. Address: %x", d_adr_o);
683 // synthesis translate_on
687 `ifdef CFG_DCACHE_ENABLED
688 if (dcache_refill_request == `TRUE)
690 // Start cache refill
691 d_adr_o <= first_address;
693 d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
696 d_cti_o <= first_cycle_type;
701 if ( (store_q_m == `TRUE)
702 && (stall_m == `FALSE)
703 `ifdef CFG_DRAM_ENABLED
704 && (dram_select_m == `FALSE)
706 `ifdef CFG_IROM_ENABLED
707 && (irom_select_m == `FALSE)
711 // Data cache is write through, so all stores go to memory
712 d_dat_o <= store_data_m;
713 d_adr_o <= load_store_address_m;
715 d_sel_o <= byte_enable_m;
718 d_cti_o <= `LM32_CTYPE_END;
720 else if ( (load_q_m == `TRUE)
721 && (wb_select_m == `TRUE)
722 && (wb_load_complete == `FALSE)
723 // stall_m will be TRUE, because stall_wb_load will be TRUE
726 // Read requested address
727 stall_wb_load <= `FALSE;
728 d_adr_o <= load_store_address_m;
730 d_sel_o <= byte_enable_m;
733 d_cti_o <= `LM32_CTYPE_END;
736 // Clear load/store complete flag when instruction leaves M stage
737 if (stall_m == `FALSE)
738 wb_load_complete <= `FALSE;
739 // When a Wishbone load first enters the M stage, we need to stall it
740 if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
741 stall_wb_load <= `TRUE;
742 // Clear stall request if load instruction is killed
743 if ((kill_m == `TRUE) || (exception_m == `TRUE))
744 stall_wb_load <= `FALSE;
748 // Pipeline registers
750 // X/M stage pipeline registers
751 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
755 sign_extend_m <= `FALSE;
757 byte_enable_m <= `FALSE;
758 store_data_m <= {`LM32_WORD_WIDTH{1'b0}};
759 `ifdef CFG_DCACHE_ENABLED
760 dcache_select_m <= `FALSE;
762 `ifdef CFG_DRAM_ENABLED
763 dram_select_m <= `FALSE;
765 `ifdef CFG_IROM_ENABLED
766 irom_select_m <= `FALSE;
768 wb_select_m <= `FALSE;
772 if (stall_m == `FALSE)
774 sign_extend_m <= sign_extend_x;
776 byte_enable_m <= byte_enable_x;
777 store_data_m <= store_data_x;
778 `ifdef CFG_DCACHE_ENABLED
779 dcache_select_m <= dcache_select_x;
781 `ifdef CFG_DRAM_ENABLED
782 dram_select_m <= dram_select_x;
784 `ifdef CFG_IROM_ENABLED
785 irom_select_m <= irom_select_x;
787 wb_select_m <= wb_select_x;
792 // M/W stage pipeline registers
793 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
798 data_w <= {`LM32_WORD_WIDTH{1'b0}};
799 sign_extend_w <= `FALSE;
805 sign_extend_w <= sign_extend_m;
809 /////////////////////////////////////////////////////
811 /////////////////////////////////////////////////////
813 // synthesis translate_off
815 // Check for non-aligned loads or stores
816 always @(posedge clk_i)
818 if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE))
820 if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0))
821 $display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
822 if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00))
823 $display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
827 // synthesis translate_on