verilog/lm32/lm32_ram.v

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  37 //                         FILE DETAILS
  38 // Project          : LatticeMico32
  39 // File             : lm32_ram.v
  40 // Title            : Pseudo dual-port RAM.
  41 // Version          : 6.1.17
  42 //                  : Initial Release
  43 // Version          : 7.0SP2, 3.0
  44 //                  : No Change
  45 // Version          : 3.1
  46 //                  : Options added to select EBRs (True-DP, Psuedo-DP, DQ, or
  47 //                  : Distributed RAM).
  48 // Version          : 3.2
  49 //                  : EBRs use SYNC resets instead of ASYNC resets.
  50 // Version          : 3.5
  51 //                  : Added read-after-write hazard resolution when using true
  52 //                  : dual-port EBRs
  53 // =============================================================================
  54
  55 `include "lm32_include.v"
  56
  57 /////////////////////////////////////////////////////
  58 // Module interface
  59 /////////////////////////////////////////////////////
  60
  61 module lm32_ram
  62   (
  63    // ----- Inputs -------
  64    read_clk,
  65    write_clk,
  66    reset,
  67    enable_read,
  68    read_address,
  69    enable_write,
  70    write_address,
  71    write_data,
  72    write_enable,
  73    // ----- Outputs -------
  74    read_data
  75    );
  76
  77 /*----------------------------------------------------------------------
  78  Parameters
  79  ----------------------------------------------------------------------*/
  80 parameter data_width = 1;               // Width of the data ports
  81 parameter address_width = 1;            // Width of the address ports
  82
  83 /*----------------------------------------------------------------------
  84  Inputs
  85  ----------------------------------------------------------------------*/
  86 input read_clk;                         // Read clock
  87 input write_clk;                        // Write clock
  88 input reset;                            // Reset
  89
  90 input enable_read;                      // Access enable
  91 input [address_width-1:0] read_address; // Read/write address
  92 input enable_write;                     // Access enable
  93 input [address_width-1:0] write_address;// Read/write address
  94 input [data_width-1:0] write_data;      // Data to write to specified address
  95 input write_enable;                     // Write enable
  96
  97 /*----------------------------------------------------------------------
  98  Outputs
  99  ----------------------------------------------------------------------*/
 100 output [data_width-1:0] read_data;      // Data read from specified addess
 101 wire   [data_width-1:0] read_data;
 102
 103 /*----------------------------------------------------------------------
 104  Internal nets and registers
 105  ----------------------------------------------------------------------*/
 106 reg [data_width-1:0]    mem[0:(1<<address_width)-1]; // The RAM
 107 reg [address_width-1:0] ra; // Registered read address
 108
 109 /*----------------------------------------------------------------------
 110  Combinational Logic
 111  ----------------------------------------------------------------------*/
 112 // Read port
 113 assign read_data = mem[ra];
 114
 115 /*----------------------------------------------------------------------
 116  Sequential Logic
 117  ----------------------------------------------------------------------*/
 118 // Write port
 119 always @(posedge write_clk)
 120   if ((write_enable == `TRUE) && (enable_write == `TRUE))
 121     mem[write_address] <= write_data;
 122
 123 // Register read address for use on next cycle
 124 always @(posedge read_clk)
 125   if (enable_read)
 126     ra <= read_address;
 127
 128 endmodule