+ url = https://github.com/enjoy-digital/VexRiscv-verilog.git
+[submodule "litex/soc/cores/cpu/minerva/verilog"]
+ path = litex/soc/cores/cpu/minerva/verilog
+ url = https://github.com/lambdaconcept/minerva
+[submodule "litex/soc/cores/cpu/rocket/verilog"]
+ path = litex/soc/cores/cpu/rocket/verilog
+ url = https://github.com/enjoy-digital/rocket-litex-verilog
+[submodule "litex/soc/cores/cpu/microwatt/sources"]
+ path = litex/soc/cores/cpu/microwatt/sources
+ url = https://github.com/antonblanchard/microwatt
+[submodule "litex/soc/cores/cpu/blackparrot/pre-alpha-release"]
+ path = litex/soc/cores/cpu/blackparrot/pre-alpha-release
+ url = https://github.com/enjoy-digital/black-parrot.git