----------
-LiteScope is small footprint and configurable embedded logic analyzer that you
-can use in your FPGA and aims to provide a a free, portable and flexible
-alternatve to vendor's solutions!
-
-LiteScope is part of LiteX libraries whose aims are to lower entry level of complex
-FPGA IP cores by providing simple, elegant and efficient implementations of
-components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
-
-The core uses simple and specific streaming buses and will provides in the future
-adapters to use standardized AXI or Avalon-ST streaming buses.
-
-Since Python is used to describe the HDL, the core is highly and easily
-configurable.
-
-LiteScope uses technologies developed in partnership with M-Labs Ltd:
- - Migen enables generating HDL with Python in an efficient way.
- - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
-
-LiteScope can be used as a Migen/MiSoC library (by simply installing it
-with the provided setup.py) or can be integrated with your standard design flow
-by generating the verilog rtl that you will use as a standard core.
-
-LiteScope produces "vcd" files that can be read in your regular waveforms viewer.
-
-Since LiteScope also provides a UART <--> Wishbone brige so you only need 2
-external Rx/Tx pins to be ready to debug or control all your Wishbone peripherals!
-
-[> Features
------------
-- IO peek and poke with LiteScopeIO
-- Logic analyser with LiteScopeLA:
- - Various triggering modules: Term, Range, Edge (add yours! :)
- - Run Length Encoder to "compress" data and increase recording depth
- - Subsampling
- - Storage qualifier
- - Data storage in block rams
-
-[> Possible improvements
--------------------------
-- add standardized interfaces (AXI, Avalon-ST)
-- add protocols analyzers
-- add signals injection/generation
-- add storage in DRAM
-- add storage in HDD with LiteSATA core (to be released soon!)
-- add Ethernet Wishbone bridge
-- add PCIe Wishbone bridge with LitePCIe (to be released soon!)
-- ... See below Support and consulting :)
-
-If you want to support these features, please contact us at florent [AT]
-enjoy-digital.fr. You can also contact our partner on the public mailing list
-devel [AT] lists.m-labs.hk.
-
-
-[> Getting started
-------------------
-1. Install Python3 and your vendor's software
-
-2. Obtain Migen and install it:
- git clone https://github.com/m-labs/migen
- cd migen
- python3 setup.py install
- cd ..
-
-3. Obtain MiSoC and install it:
- git clone https://github.com/m-labs/misoc --recursive
- cd misoc
- python3 setup.py install
- cd ..
-
-Note: in case you have issues with Migen/MiSoC, please retry
-with our forks at:
- https://github.com/enjoy-digital/misoc
- https://github.com/enjoy-digital/migen
-until new features are merged.
-
-4. Obtain LiteScope and install it:
- git clone https://github.com/enjoy-digital/litescope
-
-5. Build and load test design:
- python3 make.py -s [platform] all
- Supported platforms are the one altready supported by Mibuild:
- de0nano, m1, mixxeo, kc705, zedboard...
-
-6. Test design:
- go to ./test directory and run:
- python3 test_io.py
- python3 test_la.py
-
-[> Simulations:
- XXX convert simulations
-
-[> Tests :
- XXX convert tests