+ def _constrain(self, platform):
+ # The asynchronous input to a MultiReg is a false path
+ platform.add_platform_command(
+ "set_false_path -quiet "
+ "-to [get_nets -filter {{mr_ff == TRUE}}]"
+ )
+ # The asychronous reset input to the AsyncResetSynchronizer is a false
+ # path
+ platform.add_platform_command(
+ "set_false_path -quiet "
+ "-to [get_pins -filter {{REF_PIN_NAME == PRE}} "
+ "-of [get_cells -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]"
+ )
+ # clock_period-2ns to resolve metastability on the wire between the
+ # AsyncResetSynchronizer FFs
+ platform.add_platform_command(
+ "set_max_delay 2 -quiet "
+ "-from [get_pins -filter {{REF_PIN_NAME == Q}} "
+ "-of [get_cells -filter {{ars_ff1 == TRUE}}]] "
+ "-to [get_pins -filter {{REF_PIN_NAME == D}} "
+ "-of [get_cells -filter {{ars_ff2 == TRUE}}]]"
+ )
+