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Added English Language description for stwup instruction
[openpower-isa.git]
/
openpower
/
isa
/
pifixedstore.mdwn
diff --git
a/openpower/isa/pifixedstore.mdwn
b/openpower/isa/pifixedstore.mdwn
index 627fb24a21ccbc479814e3f9e11996e5ae835189..8a45cd96858ca026ec0957baa7f2b50ec6c111c9 100644
(file)
--- a/
openpower/isa/pifixedstore.mdwn
+++ b/
openpower/isa/pifixedstore.mdwn
@@
-72,9
+72,9
@@
Pseudo-code:
Description:
Description:
-Let the effective address (EA) be the sum (RA|0)+ D.
-(RS)[48:63] are stored into the halfword in storage
-addressed by EA.
+
Let the effective address (EA) be the sum (RA|0)+ D.
+
(RS)[48:63] are stored into the halfword in storage
+
addressed by EA.
Special Registers Altered:
Special Registers Altered:
@@
-93,6
+93,16
@@
Pseudo-code:
MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
RA <- EA
MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
RA <- EA
+Description:
+
+ Let the effective address (EA) be the sum (RA)+ (RB).
+ (RS)[56:63] are stored into the byte in storage addressed
+ by EA.
+
+ EA is placed into register RA.
+
+ If RA=0, the instruction form is invalid
+
Special Registers Altered:
None
Special Registers Altered:
None
@@
-110,6
+120,16
@@
Pseudo-code:
MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
RA <- EA
MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
RA <- EA
+Description:
+
+ Let the effective address (EA) be the sum (RA)+ D.
+ (RS)[32:63] are stored into the word in storage addressed
+ by EA.
+
+ EA is placed into register RA.
+
+ If RA=0, the instruction form is invalid.
+
Special Registers Altered:
None
Special Registers Altered:
None